This v4 reworks the initial NEORV32 submissions.
The series introduces:
* a minimal NEORV32 RV32 CPU type and vendor CSR hook,
* the SYSINFO MMIO block,
* a small UART device,
* an SPI controller with command-mode chip-select,
* and the 'neorv32' RISC-V board wiring the above, plus docs.
Tested by booting the NEORV32 bootloader as -bios and chaining into a
Hello World from an MTD-backed SPI flash image, with UART on stdio.
Changes since v3:
* Clean-up and fix documentation build errors
* Fixed extra blank lines
Thanks Daniel for the review and for providing the documentation fix suggestions.
Changes since v2:
* Clean-up all errors and most of the warnings generated by scripts/checkpatch.pl
* Sync with master, fix compile error
* No intentional functional changes; only file organization and clarity.
* Kept default.mak entry off by default (n).
Patch layout
============
1/5 target/riscv: add NEORV32 RV32 CPU type and vendor CSR hooks
2/5 hw/misc: add NEORV32 SYSINFO block (CLK/MISC/SOC/CACHE)
3/5 hw/char: add NEORV32 UART (CTRL/DATA, fifo, chardev)
4/5 hw/ssi: add NEORV32 SPI controller (SSI master, CS command)
5/5 hw/riscv: introduce 'neorv32' board, docs, and riscv32 device config
Quick usage
===========
$ ./configure --target-list=riscv32-softmmu --enable-debug --enable-fdt
$ make -j$(nproc)
Prepare a flash image (64MiB) and place your app at 4MiB offset:
$ dd if=/dev/zero of=$HOME/flash_contents.bin bs=1 count=$((0x04000000))
$ dd if=/path/to/neorv32_exe.bin of=$HOME/flash_contents.bin \\
bs=1 seek=$((0x00400000)) conv=notrunc
Run bootloader and chain-load your app:
$ ./build/qemu-system-riscv32 -nographic -machine neorv32 \\
-bios /path/to/neorv32/bootloader/neorv32_raw_exe.bin \\
-drive file=$HOME/flash_contents.bin,if=mtd,format=raw
Debugging:
$ ... -s -S # gdbstub on :1234, start paused
Thanks for reviewing!
Michael
Michael (5):
target/riscv: add NEORV32 RV32 CPU type and vendor CSR hooks
hw/misc: add NEORV32 SYSINFO block (CLK/MISC/SOC/CACHE)
hw/char: add NEORV32 UART (CTRL/DATA, fifo, chardev)
hw/ssi: add NEORV32 SPI controller (SSI master, CS command)
hw/riscv: introduce 'neorv32' board, docs, and riscv32 device config
configs/devices/riscv32-softmmu/default.mak | 1 +
docs/system/riscv/neorv32.rst | 112 +++++
docs/system/target-riscv.rst | 1 +
hw/char/Kconfig | 3 +
hw/char/meson.build | 1 +
hw/char/neorv32_uart.c | 285 ++++++++++++
hw/misc/Kconfig | 2 +
hw/misc/meson.build | 1 +
hw/misc/neorv32_sysinfo.c | 201 ++++++++
hw/misc/neorv32_sysinfo.h | 88 ++++
hw/misc/neorv32_sysinfo_rtl.h | 239 ++++++++++
hw/riscv/Kconfig | 8 +
hw/riscv/meson.build | 1 +
hw/riscv/neorv32.c | 215 +++++++++
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
hw/ssi/neorv32_spi.c | 478 ++++++++++++++++++++
include/hw/char/neorv32_uart.h | 54 +++
include/hw/riscv/neorv32.h | 54 +++
include/hw/ssi/neorv32_spi.h | 57 +++
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 17 +
target/riscv/cpu.h | 3 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/cpu_vendorid.h | 2 +
target/riscv/meson.build | 1 +
target/riscv/neorv32_csr.c | 40 ++
28 files changed, 1872 insertions(+)
create mode 100644 docs/system/riscv/neorv32.rst
create mode 100644 hw/char/neorv32_uart.c
create mode 100644 hw/misc/neorv32_sysinfo.c
create mode 100644 hw/misc/neorv32_sysinfo.h
create mode 100644 hw/misc/neorv32_sysinfo_rtl.h
create mode 100644 hw/riscv/neorv32.c
create mode 100644 hw/ssi/neorv32_spi.c
create mode 100644 include/hw/char/neorv32_uart.h
create mode 100644 include/hw/riscv/neorv32.h
create mode 100644 include/hw/ssi/neorv32_spi.h
create mode 100644 target/riscv/neorv32_csr.c
--
2.51.1