Introduce a new common realize function aspeed_soc_ast10x0_realize()
for AST10x0 series SoCs. The shared initialization and realization logic
is now placed in this common function to improve code reuse and reduce
duplication between different SoCs in the same family.
The AST1030 realization function aspeed_soc_ast1030_realize() is
updated to call the new common routine and then perform realization of
its own specific devices such as LPC and PECI, which are not present on
future SoCs like AST1060.
This refactor simplifies maintenance and prepares the framework for
adding AST1060 support.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast10x0.c | 128 ++++++++++++++++++++++------------------
1 file changed, 70 insertions(+), 58 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 5941ebe00c..5bbe16af24 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -190,10 +190,9 @@ static void aspeed_soc_ast1030_init(Object *obj)
object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
}
-static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
+static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
{
- Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
- AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCState *s = ASPEED_SOC(a);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
Error *err = NULL;
@@ -203,7 +202,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!clock_has_source(s->sysclk)) {
error_setg(errp, "sysclk clock must be wired up by the board code");
- return;
+ return false;
}
/* General I/O memory space to catch all unimplemented device */
@@ -216,7 +215,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
"aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
0x40000);
- /* AST1030 CPU Core */
+ /* AST10x0 CPU Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
qdev_prop_set_string(armv7m, "cpu-type",
@@ -232,7 +231,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
if (err != NULL) {
error_propagate(errp, err);
- return;
+ return false;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
@@ -241,14 +240,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sc->secsram_size, &err);
if (err != NULL) {
error_propagate(errp, err);
- return;
+ return false;
}
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
&s->secsram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
sc->memmap[ASPEED_DEV_SCU]);
@@ -258,7 +257,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
sc->memmap[ASPEED_DEV_I2C]);
@@ -271,7 +270,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* I3C */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0,
sc->memmap[ASPEED_DEV_I3C]);
@@ -282,50 +281,11 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
}
- /* PECI */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
- return;
- }
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
- sc->memmap[ASPEED_DEV_PECI]);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
- aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI));
-
- /* LPC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
- return;
- }
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
- sc->memmap[ASPEED_DEV_LPC]);
-
- /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
- aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC));
-
- /*
- * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
- */
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
- qdev_get_gpio_in(DEVICE(&a->armv7m),
- sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
-
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
- qdev_get_gpio_in(DEVICE(&a->armv7m),
- sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
-
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
- qdev_get_gpio_in(DEVICE(&a->armv7m),
- sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
-
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
- qdev_get_gpio_in(DEVICE(&a->armv7m),
- sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
-
/* UART */
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
- return;
+ return false;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_ast1030_get_irq(s, uart));
@@ -335,7 +295,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
@@ -346,7 +306,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* ADC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
sc->memmap[ASPEED_DEV_ADC]);
@@ -357,7 +317,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
sc->memmap[ASPEED_DEV_FMC]);
@@ -371,7 +331,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
object_property_set_link(OBJECT(&s->spi[i]), "dram",
OBJECT(&s->sram), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_DEV_SPI1 + i]);
@@ -383,7 +343,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* Secure Boot Controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0,
sc->memmap[ASPEED_DEV_SBC]);
@@ -392,7 +352,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
@@ -407,14 +367,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
- return;
+ return false;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
@@ -442,6 +402,58 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),
"aspeed.jtag",
sc->memmap[ASPEED_DEV_JTAG1], 0x20);
+
+ return true;
+}
+
+static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ if (!aspeed_soc_ast10x0_realize(a, errp)) {
+ return;
+ }
+
+ /* PECI */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
+ sc->memmap[ASPEED_DEV_PECI]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
+ aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI));
+
+ /* LPC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
+ sc->memmap[ASPEED_DEV_LPC]);
+
+ /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
+ aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC));
+
+ /*
+ * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
}
static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
--
2.43.0On 11/6/25 09:49, Jamin Lin wrote: > Introduce a new common realize function aspeed_soc_ast10x0_realize() > for AST10x0 series SoCs. The shared initialization and realization logic > is now placed in this common function to improve code reuse and reduce > duplication between different SoCs in the same family. > > The AST1030 realization function aspeed_soc_ast1030_realize() is > updated to call the new common routine and then perform realization of > its own specific devices such as LPC and PECI, which are not present on > future SoCs like AST1060. > > This refactor simplifies maintenance and prepares the framework for > adding AST1060 support. > > No functional changes. > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > --- > hw/arm/aspeed_ast10x0.c | 128 ++++++++++++++++++++++------------------ > 1 file changed, 70 insertions(+), 58 deletions(-) LGTM, Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C.
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