hw/gpio: Add Aspeed Serial GPIO (SGPIO) controller model

[PATCH 0/2] hw/gpio: Add Aspeed Serial GPIO (SGPIO) controller model

Yubin Zou posted 2 patches 1 week ago

Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251106-aspeed-sgpio-v1-0-b026093716fa@google.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>

hw/arm/aspeed_ast10x0.c          |   6 +-
hw/arm/aspeed_ast27x0.c          |  26 +++
hw/gpio/aspeed_sgpio.c           | 349 +++++++++++++++++++++++++++++++++++++++
hw/gpio/meson.build              |   1 +
include/hw/arm/aspeed_soc.h      |   8 +-
include/hw/gpio/aspeed_sgpio.h   |  68 ++++++++
tests/qtest/ast2700-sgpio-test.c | 152 +++++++++++++++++
tests/qtest/meson.build          |   1 +
8 files changed, 606 insertions(+), 5 deletions(-)

Expand all Fold all

[PATCH 0/2] hw/gpio: Add Aspeed Serial GPIO (SGPIO) controller model

Posted by Yubin Zou 1 week ago

This series introduces a model for the Aspeed Serial GPIO (SGPIO) controller,
commonly found on Aspeed SoCs such as the AST2700. The SGPIO peripheral
provides a large number of GPIO pins that can be controlled and monitored
serially.

Improvement to QEMU:
These patches enhance QEMU's hardware emulation capabilities for platforms
using Aspeed SoCs, particularly for BMC simulations. By modeling the SGPIO
controller, QEMU can more accurately represent the hardware, allowing for
better development and testing of firmware and software that relies on these
GPIOs for various functions like sensor monitoring, presence detect, and
system control signals.

Impact (Before/After):

Before:
QEMU lacked a model for the Aspeed SGPIO controller. Any guest software
attempting to interact with the SGPIO register space would find no device.
Firmware features depending on SGPIO pin states or interrupts could not be
tested in QEMU.

After:
QEMU emulates the Aspeed SGPIO controller on supported machines (e.g.,
ast2700-evb).
- Guest firmware can configure SGPIO pins, set output values, and read input
  values through the memory-mapped registers.
- External entities (like test scripts or other QEMU components) can interact
  with the pins via QOM properties (e.g., to simulate external signal changes).
  Path example: /machine/soc/sgpio[0]/sgpio0
- The model generates interrupts based on input pin transitions, according to
  the configured mode (level/edge), enabling testing of interrupt handlers.

Signed-off-by: Yubin Zou <yubinz@google.com>
---
Yubin Zou (2):
      hw/gpio: Add the skeleton of Aspeed Serial gpio
      hw/gpio Add the Interrupt logic to Aspeed Serial gpio

 hw/arm/aspeed_ast10x0.c          |   6 +-
 hw/arm/aspeed_ast27x0.c          |  26 +++
 hw/gpio/aspeed_sgpio.c           | 349 +++++++++++++++++++++++++++++++++++++++
 hw/gpio/meson.build              |   1 +
 include/hw/arm/aspeed_soc.h      |   8 +-
 include/hw/gpio/aspeed_sgpio.h   |  68 ++++++++
 tests/qtest/ast2700-sgpio-test.c | 152 +++++++++++++++++
 tests/qtest/meson.build          |   1 +
 8 files changed, 606 insertions(+), 5 deletions(-)
---
base-commit: 917ac07f9aef579b9538a81d45f45850aba42906
change-id: 20251105-aspeed-sgpio-1d49de6cea66

Best regards,
-- 
Yubin Zou <yubinz@google.com>