On Wed, Nov 5, 2025 at 3:25 PM Taylor Simpson <ltaylorsimpson@gmail.com>
wrote:
> Currently, any instruction that writes USR disables short-circuiting a
> packet. When the write is implicit, we can allow the short-circuit.
>
This series is now queued at https://github.com/quic/qemu branch
hex-next-express
>
> Changes in v2:
> - Properly handle implicit USR writes when packet commit is necessary
> - Added test case
>
> Changes in v3:
> - Address feedback from Brian Cain <brian.cain@oss.qualcomm.com>
> Use symbolic/named operands in inline asm
> - Added more packet test cases
>
>
> Taylor Simpson (3):
> Hexagon (target/hexagon) Add pkt_need_commit argument to arch_fpop_end
> Hexagon (target/hexagon) Implicit writes to USR don't force packet
> commit
> Hexagon (tests/tcg/hexagon) Add test for USR changes in packet
>
> target/hexagon/arch.h | 2 +-
> target/hexagon/gen_tcg.h | 114 ++++++------
> target/hexagon/helper.h | 114 ++++++------
> target/hexagon/translate.h | 1 +
> target/hexagon/arch.c | 3 +-
> target/hexagon/op_helper.c | 287 +++++++++++++++++------------
> target/hexagon/translate.c | 35 ++--
> tests/tcg/hexagon/usr.c | 54 ++++++
> target/hexagon/gen_helper_funcs.py | 8 +-
> target/hexagon/gen_tcg_funcs.py | 4 +
> 10 files changed, 371 insertions(+), 251 deletions(-)
>
> --
> 2.43.0
>
>