docs/system/devices/cxl.rst | 23 +++ hw/cxl/cxl-component-utils.c | 211 ++++++++++++++++------ hw/cxl/cxl-host.c | 2 +- hw/mem/cxl_type3.c | 15 +- hw/pci-bridge/cxl_downstream.c | 10 +- hw/pci-bridge/cxl_root_port.c | 11 +- hw/pci-bridge/cxl_upstream.c | 18 +- hw/pci-bridge/gen_pcie_root_port.c | 1 + hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci/pcie.c | 23 ++- include/hw/cxl/cxl_component.h | 87 +++++++-- include/hw/cxl/cxl_device.h | 4 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + include/hw/pci/pcie.h | 2 +- include/hw/pci/pcie_port.h | 1 + qapi/machine.json | 3 +- qemu-options.hx | 4 +- 17 files changed, 319 insertions(+), 99 deletions(-)
The following allows support for component basic back invalidation discovery
and config, by exposing the BI routing table and decoder registers. Instead
of going the type2[0] route, this series proposes adding support for type3
hdm-db, which allows a more direct way of supporting BI in qemu.
Changes from v3 (https://lore.kernel.org/all/20250930032153.1127773-1-dave@stgolabs.net/):
o Fix Flexbus caps bits in patch 1. (Jonathan)
o Flipped the bi arg to true for hard-configured components in patch 4 (Jonathan).
o Expose the BI routing table only if the sw upstream port is in Flit mode.
o Removed the mem-path= arg in the documentation as it deals with volatile (Donjoo).
Changes from v2 (https://lore.kernel.org/linux-cxl/20250811033405.332295-1-dave@stgolabs.net/):
o Renamed 256b-flit to x-256b-flit (mst)
o Added a brief description of flit mode in patch 1 changelog (Markus)
o Added missing hdm-db parameter which went missing in v2.
o Replaced the new CXL3_TYPE3_DEVICE with passing 'bi' params. (Jonathan)
o Fixed writemask bits in patch 4. (Jonathan)
o Misc cleanups in patch 4. (Jonathan)
o New patch 5 to remove register special_ops read() cb. (Jonathan)
Changes from v1 (https://lore.kernel.org/qemu-devel/20250806055708.196851-1-dave@stgolabs.net/):
o Further lnk training in patch 1. (Jonathan)
o Flit parameter changed to bool in patch 1. (Jonathan)
o Do not set 68B in component Flexbus Port when in flitmode in patch 1.
o Doc build fixlet in patch 3.
o Pass the exact type3 type in cxl_component_create_dvsec() - unused, but better
for keeping track, in patch 4.
o Change doc example to volatile device in patch 4.
Changes from rfc (https://lore.kernel.org/qemu-devel/20250729165441.1898150-1-dave@stgolabs.net/):
o Added 256b-flit parameter, per Jonathan.
o Added window restrictions changes.
o Dropped rfc tag.
Patch 1 introduces the flit mode parameter.
Patch 2 is lifted from Ira's series with some small (but non-trivial) changes.
Patch 3 updates the cfmw restrictions option.
Patch 4 adds BI decoder/rt register support to enable type3 HDM-DB.
Patch 5 is a small cleanup.
Testing wise, this has passed relevant kernel side BI register IO flows for
BI-ID setup and deallocation.
The next step for this would be to add UIO support to qemu.
Applies against branch 'origin/cxl-2025-10-03-draft' from Jonathan's repository.
Thanks!
Davidlohr Bueso (4):
hw/pcie: Support enabling flit mode
hw/cxl: Allow BI by default in Window restrictions
hw/cxl: Support type3 HDM-DB
hw/cxl: Remove register special_ops->read()
Ira Weiny (1):
hw/cxl: Refactor component register initialization
docs/system/devices/cxl.rst | 23 +++
hw/cxl/cxl-component-utils.c | 211 ++++++++++++++++------
hw/cxl/cxl-host.c | 2 +-
hw/mem/cxl_type3.c | 15 +-
hw/pci-bridge/cxl_downstream.c | 10 +-
hw/pci-bridge/cxl_root_port.c | 11 +-
hw/pci-bridge/cxl_upstream.c | 18 +-
hw/pci-bridge/gen_pcie_root_port.c | 1 +
hw/pci-bridge/pci_expander_bridge.c | 2 +-
hw/pci/pcie.c | 23 ++-
include/hw/cxl/cxl_component.h | 87 +++++++--
include/hw/cxl/cxl_device.h | 4 +
include/hw/pci-bridge/cxl_upstream_port.h | 1 +
include/hw/pci/pcie.h | 2 +-
include/hw/pci/pcie_port.h | 1 +
qapi/machine.json | 3 +-
qemu-options.hx | 4 +-
17 files changed, 319 insertions(+), 99 deletions(-)
--
2.39.5
ping? If there are no further issues, could this be picked up into your jic23 tree? Thanks, Davidlohr
On Mon, 15 Dec 2025 17:12:11 -0800 Davidlohr Bueso <dave@stgolabs.net> wrote: > ping? If there are no further issues, could this be picked up into > your jic23 tree? > > Thanks, > Davidlohr > Hi Davidlohr, I'm just waiting on the 10.2 release before bringing my tree up to date and reposting the various series that I consider ready which didn't get merged in 10.2. Then I'll figure out where in the tree to push these in. I might do the leg work for that before the release, but given that should happen shortly I'll not push a tree out on gitlab until after that. Jonathan
On Wed, 17 Dec 2025 13:59:30 +0000 Jonathan Cameron via <qemu-devel@nongnu.org> wrote: > On Mon, 15 Dec 2025 17:12:11 -0800 > Davidlohr Bueso <dave@stgolabs.net> wrote: > > > ping? If there are no further issues, could this be picked up into > > your jic23 tree? > > > > Thanks, > > Davidlohr > > > Hi Davidlohr, > > I'm just waiting on the 10.2 release before bringing my tree up to > date and reposting the various series that I consider ready which > didn't get merged in 10.2. > > Then I'll figure out where in the tree to push these in. I might > do the leg work for that before the release, but given that should > happen shortly I'll not push a tree out on gitlab until after that. > > Jonathan > Hi Davidlohr, Seems the release has been tagged, so I've just rebased and pushed out a draft tree as cxl-2025-12-23-draft Draft because it is very very lightly tested so far. On that I've merged in these patches with a few tweaks + added the table test updates. If you get a minute to take a look please do. It's behind a couple of left over series from earlier cycles but my intent is to post it for reviews prior to merge shortly. That may not include in the restrictions control qapi as I think that interface may need more thought. For now I've added a patch that just enables BI always for CFMWSes. Jonathan
On Tue, 23 Dec 2025, Jonathan Cameron wrote: >On Wed, 17 Dec 2025 13:59:30 +0000 >Jonathan Cameron via <qemu-devel@nongnu.org> wrote: > >Seems the release has been tagged, so I've just rebased and pushed >out a draft tree as cxl-2025-12-23-draft >Draft because it is very very lightly tested so far. Thank you for picking this up, 'draft' is fine with me :) However, I am not seeing this new branch in your tree(?) > >On that I've merged in these patches with a few tweaks + added the >table test updates. If you get a minute to take a look please do. > >It's behind a couple of left over series from earlier cycles but my >intent is to post it for reviews prior to merge shortly. That >may not include in the restrictions control qapi as I think that interface >may need more thought. For now I've added a patch that just enables >BI always for CFMWSes. Makes sense. Thanks, Davidlohr
On Tue, 30 Dec 2025 10:23:30 -0800 Davidlohr Bueso <dave@stgolabs.net> wrote: > On Tue, 23 Dec 2025, Jonathan Cameron wrote: > > >On Wed, 17 Dec 2025 13:59:30 +0000 > >Jonathan Cameron via <qemu-devel@nongnu.org> wrote: > > > >Seems the release has been tagged, so I've just rebased and pushed > >out a draft tree as cxl-2025-12-23-draft > >Draft because it is very very lightly tested so far. > > Thank you for picking this up, 'draft' is fine with me :) > However, I am not seeing this new branch in your tree(?) Hi Davidlohr, Happy new year. Hmm. Could have sworn I pushed i out... Guess messed that up :( Note there is a stray change in there for an unrelated tests tree that I've tidied up in my local tree. I'll push a new tree out next week but assuming this series isn't otherwise messed up by me, I'd like to email this out as something I think is ready to merge before I do that. If you spot anything bad with this I might shuffle things around to put the physical port commands set ahead of it. Jonathan > > > > >On that I've merged in these patches with a few tweaks + added the > >table test updates. If you get a minute to take a look please do. > > > >It's behind a couple of left over series from earlier cycles but my > >intent is to post it for reviews prior to merge shortly. That > >may not include in the restrictions control qapi as I think that interface > >may need more thought. For now I've added a patch that just enables > >BI always for CFMWSes. > > Makes sense. > > Thanks, > Davidlohr >
Davidlohr Bueso <dave@stgolabs.net> writes: > The following allows support for component basic back invalidation discovery > and config, by exposing the BI routing table and decoder registers. Instead > of going the type2[0] route, this series proposes adding support for type3 > hdm-db, which allows a more direct way of supporting BI in qemu. [...] > Applies against branch 'origin/cxl-2025-10-03-draft' from Jonathan's repository. URL? [...]
On Tue, 16 Dec 2025, Markus Armbruster wrote:
>Davidlohr Bueso <dave@stgolabs.net> writes:
>
>> The following allows support for component basic back invalidation discovery
>> and config, by exposing the BI routing table and decoder registers. Instead
>> of going the type2[0] route, this series proposes adding support for type3
>> hdm-db, which allows a more direct way of supporting BI in qemu.
>
>[...]
>
>> Applies against branch 'origin/cxl-2025-10-03-draft' from Jonathan's repository.
>
>URL?
That would be:
https://gitlab.com/jic23/qemu/-/commits/cxl-2025-10-03-draft
Davidlohr Bueso <dave@stgolabs.net> writes: > On Tue, 16 Dec 2025, Markus Armbruster wrote: > >>Davidlohr Bueso <dave@stgolabs.net> writes: >> >>> The following allows support for component basic back invalidation discovery >>> and config, by exposing the BI routing table and decoder registers. Instead >>> of going the type2[0] route, this series proposes adding support for type3 >>> hdm-db, which allows a more direct way of supporting BI in qemu. >> >>[...] >> >>> Applies against branch 'origin/cxl-2025-10-03-draft' from Jonathan's repository. >> >>URL? > > That would be: > https://gitlab.com/jic23/qemu/-/commits/cxl-2025-10-03-draft Have these patches been posted to the list? If yes, Message-Id or archive URL, please.
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