Improve USR handling

[PATCH 0/2] Improve USR handling

Taylor Simpson posted 2 patches 2 weeks ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20251031021411.111365-1-ltaylorsimpson@gmail.com

Maintainers: Brian Cain <brian.cain@oss.qualcomm.com>

target/hexagon/arch.h              |   2 +-
target/hexagon/gen_tcg.h           | 114 ++++++------
target/hexagon/helper.h            | 114 ++++++------
target/hexagon/arch.c              |   3 +-
target/hexagon/op_helper.c         | 287 +++++++++++++++++------------
target/hexagon/translate.c         |  14 +-
target/hexagon/gen_helper_funcs.py |   8 +-
target/hexagon/gen_tcg_funcs.py    |   4 +
8 files changed, 295 insertions(+), 251 deletions(-)

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[PATCH 0/2] Improve USR handling

Posted by Taylor Simpson 2 weeks ago

Currently, any instruction that writes USR disables short-circuiting a
packet.  When the write is implicit, we can allow the short-circuit.

Taylor Simpson (2):
  Hexagon (target/hexagon) Add pkt_need_commit argument to arch_fpop_end
  Hexagon (target/hexagon) Implicit writes to USR don't force packet
    commit

 target/hexagon/arch.h              |   2 +-
 target/hexagon/gen_tcg.h           | 114 ++++++------
 target/hexagon/helper.h            | 114 ++++++------
 target/hexagon/arch.c              |   3 +-
 target/hexagon/op_helper.c         | 287 +++++++++++++++++------------
 target/hexagon/translate.c         |  14 +-
 target/hexagon/gen_helper_funcs.py |   8 +-
 target/hexagon/gen_tcg_funcs.py    |   4 +
 8 files changed, 295 insertions(+), 251 deletions(-)

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2.43.0