[PATCH v4 29/33] target/riscv: Fix size of mseccfg

Anton Johansson via posted 33 patches 2 weeks, 4 days ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Laurent Vivier <laurent@vivier.eu>, Christoph Muellner <christoph.muellner@vrull.eu>, Michael Tokarev <mjt@tls.msk.ru>
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[PATCH v4 29/33] target/riscv: Fix size of mseccfg
Posted by Anton Johansson via 2 weeks, 4 days ago
mseccfg is defined in version 20250508 of the privileged specification
to be 64 bits in size.  Update relevant function arguments.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu.h | 2 +-
 target/riscv/pmp.h | 4 ++--
 target/riscv/pmp.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 153480846a..cc40d6c86c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -464,7 +464,7 @@ struct CPUArchState {
 
     /* physical memory protection */
     pmp_table_t pmp_state;
-    target_ulong mseccfg;
+    uint64_t mseccfg;
 
     /* trigger module */
     uint16_t mcontext;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 271cf24169..e322904637 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -69,8 +69,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
                       target_ulong val);
 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
 
-void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
-target_ulong mseccfg_csr_read(CPURISCVState *env);
+void mseccfg_csr_write(CPURISCVState *env, uint64_t val);
+uint64_t mseccfg_csr_read(CPURISCVState *env);
 
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
                        target_ulong val);
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3ef62d26ad..0b23b4b8ed 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -643,7 +643,7 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
 /*
  * Handle a write to a mseccfg CSR
  */
-void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+void mseccfg_csr_write(CPURISCVState *env, uint64_t val)
 {
     int i;
     uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
@@ -689,7 +689,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
 /*
  * Handle a read from a mseccfg CSR
  */
-target_ulong mseccfg_csr_read(CPURISCVState *env)
+uint64_t mseccfg_csr_read(CPURISCVState *env)
 {
     trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
     return env->mseccfg;
-- 
2.51.0


Re: [PATCH v4 29/33] target/riscv: Fix size of mseccfg
Posted by Alistair Francis 2 weeks ago
On Tue, Oct 28, 2025 at 4:23 AM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> mseccfg is defined in version 20250508 of the privileged specification
> to be 64 bits in size.  Update relevant function arguments.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h | 2 +-
>  target/riscv/pmp.h | 4 ++--
>  target/riscv/pmp.c | 4 ++--
>  3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 153480846a..cc40d6c86c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -464,7 +464,7 @@ struct CPUArchState {
>
>      /* physical memory protection */
>      pmp_table_t pmp_state;
> -    target_ulong mseccfg;
> +    uint64_t mseccfg;
>
>      /* trigger module */
>      uint16_t mcontext;
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index 271cf24169..e322904637 100644
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -69,8 +69,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
>                        target_ulong val);
>  target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
>
> -void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
> -target_ulong mseccfg_csr_read(CPURISCVState *env);
> +void mseccfg_csr_write(CPURISCVState *env, uint64_t val);
> +uint64_t mseccfg_csr_read(CPURISCVState *env);
>
>  void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
>                         target_ulong val);
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 3ef62d26ad..0b23b4b8ed 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -643,7 +643,7 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
>  /*
>   * Handle a write to a mseccfg CSR
>   */
> -void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> +void mseccfg_csr_write(CPURISCVState *env, uint64_t val)
>  {
>      int i;
>      uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
> @@ -689,7 +689,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
>  /*
>   * Handle a read from a mseccfg CSR
>   */
> -target_ulong mseccfg_csr_read(CPURISCVState *env)
> +uint64_t mseccfg_csr_read(CPURISCVState *env)
>  {
>      trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
>      return env->mseccfg;
> --
> 2.51.0
>
>