[v4] single-binary: Make riscv cpu.h target independent

[PATCH v4 18/33] target/riscv: Fix size of excp_uw2

Anton Johansson via posted 33 patches 2 weeks, 4 days ago

Diff against v1 v2 v3 v5
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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Laurent Vivier <laurent@vivier.eu>, Christoph Muellner <christoph.muellner@vrull.eu>, Michael Tokarev <mjt@tls.msk.ru>

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[PATCH v4 18/33] target/riscv: Fix size of excp_uw2

Posted by Anton Johansson via 2 weeks, 4 days ago

Fix to 64 bits to match size of instruction start words.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1e4128128b..f901608d0e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -258,7 +258,7 @@ struct CPUArchState {
     /* shadow stack register for zicfiss extension */
     uint64_t ssp;
     /* env place holder for extra word 2 during unwind */
-    target_ulong excp_uw2;
+    uint64_t excp_uw2;
     /* sw check code for sw check exception */
     target_ulong sw_check_code;
 #ifdef CONFIG_USER_ONLY
-- 
2.51.0

Re: [PATCH v4 18/33] target/riscv: Fix size of excp_uw2

Posted by Alistair Francis 2 weeks ago

On Tue, Oct 28, 2025 at 4:25 AM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> Fix to 64 bits to match size of instruction start words.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1e4128128b..f901608d0e 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -258,7 +258,7 @@ struct CPUArchState {
>      /* shadow stack register for zicfiss extension */
>      uint64_t ssp;
>      /* env place holder for extra word 2 during unwind */
> -    target_ulong excp_uw2;
> +    uint64_t excp_uw2;
>      /* sw check code for sw check exception */
>      target_ulong sw_check_code;
>  #ifdef CONFIG_USER_ONLY
> --
> 2.51.0
>
>