[v2] single-binary: Prepare hw/riscv for single compilation

[PATCH v2 2/3] hw/riscv: Replace target_ulong uses

Posted by Anton Johansson via 2 weeks, 4 days ago

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 hw/riscv/riscv-iommu.c | 6 ++++--
 hw/riscv/riscv_hart.c  | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index b33c7fe325..f8656ec04b 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -26,6 +26,8 @@
 #include "migration/vmstate.h"
 #include "qapi/error.h"
 #include "qemu/timer.h"
+#include "qemu/target-info.h"
+#include "qemu/bitops.h"
 
 #include "cpu_bits.h"
 #include "riscv-iommu.h"
@@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
             const uint64_t va_mask = (1ULL << va_len) - 1;
 
             if (pass == S_STAGE && va_len > 32) {
-                target_ulong mask, masked_msbs;
+                uint64_t mask, masked_msbs;
 
-                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
+                mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
                 masked_msbs = (addr >> (va_len - 1)) & mask;
 
                 if (masked_msbs != 0 && masked_msbs != mask) {
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index c7e98a4308..65d2c92018 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **words)
         g_assert(rc == 0);
         csr_call(words[1], cpu, csr, &val);
 
-        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
+        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
 
         return true;
     }

-- 
2.51.0

Re: [PATCH v2 2/3] hw/riscv: Replace target_ulong uses

Posted by Alistair Francis 2 weeks, 1 day ago

On Mon, Oct 27, 2025 at 10:35 PM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/riscv-iommu.c | 6 ++++--
>  hw/riscv/riscv_hart.c  | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe325..f8656ec04b 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -26,6 +26,8 @@
>  #include "migration/vmstate.h"
>  #include "qapi/error.h"
>  #include "qemu/timer.h"
> +#include "qemu/target-info.h"
> +#include "qemu/bitops.h"
>
>  #include "cpu_bits.h"
>  #include "riscv-iommu.h"
> @@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
>              const uint64_t va_mask = (1ULL << va_len) - 1;
>
>              if (pass == S_STAGE && va_len > 32) {
> -                target_ulong mask, masked_msbs;
> +                uint64_t mask, masked_msbs;
>
> -                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
> +                mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
>                  masked_msbs = (addr >> (va_len - 1)) & mask;
>
>                  if (masked_msbs != 0 && masked_msbs != mask) {
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index c7e98a4308..65d2c92018 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **words)
>          g_assert(rc == 0);
>          csr_call(words[1], cpu, csr, &val);
>
> -        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
> +        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
>
>          return true;
>      }
>
> --
> 2.51.0
>
>

Re: [PATCH v2 2/3] hw/riscv: Replace target_ulong uses

Posted by Philippe Mathieu-Daudé 2 weeks, 2 days ago

On 27/10/25 13:35, Anton Johansson wrote:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   hw/riscv/riscv-iommu.c | 6 ++++--
>   hw/riscv/riscv_hart.c  | 2 +-
>   2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe325..f8656ec04b 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -26,6 +26,8 @@
>   #include "migration/vmstate.h"
>   #include "qapi/error.h"
>   #include "qemu/timer.h"
> +#include "qemu/target-info.h"
> +#include "qemu/bitops.h"
>   
>   #include "cpu_bits.h"
>   #include "riscv-iommu.h"
> @@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
>               const uint64_t va_mask = (1ULL << va_len) - 1;
>   
>               if (pass == S_STAGE && va_len > 32) {
> -                target_ulong mask, masked_msbs;
> +                uint64_t mask, masked_msbs;
>   
> -                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
> +                mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
>                   masked_msbs = (addr >> (va_len - 1)) & mask;
>   
>                   if (masked_msbs != 0 && masked_msbs != mask) {
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index c7e98a4308..65d2c92018 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **words)
>           g_assert(rc == 0);
>           csr_call(words[1], cpu, csr, &val);
>   
> -        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
> +        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
>   
>           return true;
>       }
> 

What about csr_call()?

Re: [PATCH v2 2/3] hw/riscv: Replace target_ulong uses

Posted by Anton Johansson via 2 weeks, 1 day ago

On 29/10/25, Philippe Mathieu-Daudé wrote:
> On 27/10/25 13:35, Anton Johansson wrote:
> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > Signed-off-by: Anton Johansson <anjo@rev.ng>
> > ---
> >   hw/riscv/riscv-iommu.c | 6 ++++--
> >   hw/riscv/riscv_hart.c  | 2 +-
> >   2 files changed, 5 insertions(+), 3 deletions(-)
> > 
> > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> > index b33c7fe325..f8656ec04b 100644
> > --- a/hw/riscv/riscv-iommu.c
> > +++ b/hw/riscv/riscv-iommu.c
> > @@ -26,6 +26,8 @@
> >   #include "migration/vmstate.h"
> >   #include "qapi/error.h"
> >   #include "qemu/timer.h"
> > +#include "qemu/target-info.h"
> > +#include "qemu/bitops.h"
> >   #include "cpu_bits.h"
> >   #include "riscv-iommu.h"
> > @@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
> >               const uint64_t va_mask = (1ULL << va_len) - 1;
> >               if (pass == S_STAGE && va_len > 32) {
> > -                target_ulong mask, masked_msbs;
> > +                uint64_t mask, masked_msbs;
> > -                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
> > +                mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
> >                   masked_msbs = (addr >> (va_len - 1)) & mask;
> >                   if (masked_msbs != 0 && masked_msbs != mask) {
> > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> > index c7e98a4308..65d2c92018 100644
> > --- a/hw/riscv/riscv_hart.c
> > +++ b/hw/riscv/riscv_hart.c
> > @@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **words)
> >           g_assert(rc == 0);
> >           csr_call(words[1], cpu, csr, &val);
> > -        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
> > +        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
> >           return true;
> >       }
> > 
> 
> What about csr_call()?

csr_call() is handled in the other series making cpu.h target agnostic,
there we expose 64 bit variants of reading/writing CSRs which are then
used by csr_call().

Re: [PATCH v2 2/3] hw/riscv: Replace target_ulong uses

Posted by Philippe Mathieu-Daudé 2 weeks, 1 day ago

On 30/10/25 13:32, Anton Johansson wrote:
> On 29/10/25, Philippe Mathieu-Daudé wrote:
>> On 27/10/25 13:35, Anton Johansson wrote:
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>>> ---
>>>    hw/riscv/riscv-iommu.c | 6 ++++--
>>>    hw/riscv/riscv_hart.c  | 2 +-
>>>    2 files changed, 5 insertions(+), 3 deletions(-)


>>> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
>>> index c7e98a4308..65d2c92018 100644
>>> --- a/hw/riscv/riscv_hart.c
>>> +++ b/hw/riscv/riscv_hart.c
>>> @@ -93,7 +93,7 @@ static bool csr_qtest_callback(CharBackend *chr, gchar **words)
>>>            g_assert(rc == 0);
>>>            csr_call(words[1], cpu, csr, &val);
>>> -        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
>>> +        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
>>>            return true;
>>>        }
>>>
>>
>> What about csr_call()?
> 
> csr_call() is handled in the other series making cpu.h target agnostic,
> there we expose 64 bit variants of reading/writing CSRs which are then
> used by csr_call().

Ah, good then, thanks!