hw/sysbus: Spring cleanups (part 1)

[PATCH 26/27] hw/riscv: Include missing 'system/memory.h' header
Posted by Philippe Mathieu-Daudé 2 days, 16 hours ago
"system/memory.h" header is indirectly pulled by "hw/sysbus.h".
Include it explicitly to avoid build error when refactoring the
latter.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/char/cadence_uart.h      | 1 +
 include/hw/char/ibex_uart.h         | 1 +
 include/hw/char/shakti_uart.h       | 1 +
 include/hw/char/sifive_uart.h       | 1 +
 include/hw/gpio/sifive_gpio.h       | 1 +
 include/hw/intc/riscv_aclint.h      | 1 +
 include/hw/intc/riscv_aplic.h       | 1 +
 include/hw/intc/riscv_imsic.h       | 1 +
 include/hw/intc/sifive_plic.h       | 1 +
 include/hw/misc/mchp_pfsoc_dmc.h    | 1 +
 include/hw/misc/mchp_pfsoc_ioscb.h  | 1 +
 include/hw/misc/mchp_pfsoc_sysreg.h | 1 +
 include/hw/misc/sifive_e_aon.h      | 1 +
 include/hw/misc/sifive_e_prci.h     | 1 +
 include/hw/misc/sifive_test.h       | 1 +
 include/hw/misc/sifive_u_otp.h      | 1 +
 include/hw/misc/sifive_u_prci.h     | 1 +
 include/hw/net/cadence_gem.h        | 1 +
 include/hw/riscv/opentitan.h        | 1 +
 include/hw/riscv/shakti_c.h         | 1 +
 include/hw/riscv/sifive_e.h         | 1 +
 include/hw/riscv/xiangshan_kmh.h    | 1 +
 include/hw/rtc/goldfish_rtc.h       | 1 +
 include/hw/ssi/ibex_spi_host.h      | 1 +
 include/hw/ssi/sifive_spi.h         | 1 +
 include/hw/timer/cadence_ttc.h      | 1 +
 include/hw/timer/ibex_timer.h       | 1 +
 include/hw/timer/sifive_pwm.h       | 1 +
 28 files changed, 28 insertions(+)

diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
index e7f7cd84683..d2b48313d4e 100644
--- a/include/hw/char/cadence_uart.h
+++ b/include/hw/char/cadence_uart.h
@@ -25,6 +25,7 @@
 #include "qapi/error.h"
 #include "qemu/timer.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define CADENCE_UART_RX_FIFO_SIZE           16
 #define CADENCE_UART_TX_FIFO_SIZE           16
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index 9deadf223bf..f95780063fe 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -29,6 +29,7 @@
 #include "chardev/char-fe.h"
 #include "qemu/timer.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define IBEX_UART_TX_FIFO_SIZE 16
 #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
index 526c408233f..c15b5f9c82c 100644
--- a/include/hw/char/shakti_uart.h
+++ b/include/hw/char/shakti_uart.h
@@ -27,6 +27,7 @@
 
 #include "hw/sysbus.h"
 #include "chardev/char-fe.h"
+#include "system/memory.h"
 
 #define SHAKTI_UART_BAUD        0x00
 #define SHAKTI_UART_TX          0x04
diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 0846cf62188..a46c4d12766 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -25,6 +25,7 @@
 #include "hw/sysbus.h"
 #include "qom/object.h"
 #include "qemu/fifo8.h"
+#include "system/memory.h"
 
 enum {
     SIFIVE_UART_TXFIFO        = 0,
diff --git a/include/hw/gpio/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
index fc53785c9d0..72e116252b7 100644
--- a/include/hw/gpio/sifive_gpio.h
+++ b/include/hw/gpio/sifive_gpio.h
@@ -16,6 +16,7 @@
 
 #include "hw/sysbus.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
 typedef struct SIFIVEGPIOState SIFIVEGPIOState;
diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
index 4b7406eec00..07e562fd6c1 100644
--- a/include/hw/intc/riscv_aclint.h
+++ b/include/hw/intc/riscv_aclint.h
@@ -22,6 +22,7 @@
 #define HW_RISCV_ACLINT_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define TYPE_RISCV_ACLINT_MTIMER "riscv.aclint.mtimer"
 
diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index 489b9133c26..86bbe0cf859 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -23,6 +23,7 @@
 #include "qom/object.h"
 
 #define TYPE_RISCV_APLIC "riscv.aplic"
+#include "system/memory.h"
 
 typedef struct RISCVAPLICState RISCVAPLICState;
 DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h
index 58c2aaa8dc6..4b9de5eb612 100644
--- a/include/hw/intc/riscv_imsic.h
+++ b/include/hw/intc/riscv_imsic.h
@@ -21,6 +21,7 @@
 
 #include "hw/sysbus.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_RISCV_IMSIC "riscv.imsic"
 
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index d3f45ec2481..85524711da4 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -23,6 +23,7 @@
 
 #include "hw/sysbus.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
 
diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h
index 3bc1581e0f2..d3bc38a8ddd 100644
--- a/include/hw/misc/mchp_pfsoc_dmc.h
+++ b/include/hw/misc/mchp_pfsoc_dmc.h
@@ -24,6 +24,7 @@
 #define MCHP_PFSOC_DMC_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 /* DDR SGMII PHY module */
 
diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
index 3fd3e749665..276e2a1c533 100644
--- a/include/hw/misc/mchp_pfsoc_ioscb.h
+++ b/include/hw/misc/mchp_pfsoc_ioscb.h
@@ -24,6 +24,7 @@
 #define MCHP_PFSOC_IOSCB_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 typedef struct MchpPfSoCIoscbState {
     SysBusDevice parent;
diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
index c2232bd28d0..29ea39fe5c0 100644
--- a/include/hw/misc/mchp_pfsoc_sysreg.h
+++ b/include/hw/misc/mchp_pfsoc_sysreg.h
@@ -24,6 +24,7 @@
 #define MCHP_PFSOC_SYSREG_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define MCHP_PFSOC_SYSREG_REG_SIZE  0x2000
 
diff --git a/include/hw/misc/sifive_e_aon.h b/include/hw/misc/sifive_e_aon.h
index 2ae1c4139ca..77351e2ef84 100644
--- a/include/hw/misc/sifive_e_aon.h
+++ b/include/hw/misc/sifive_e_aon.h
@@ -21,6 +21,7 @@
 
 #include "hw/sysbus.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_SIFIVE_E_AON "riscv.sifive.e.aon"
 OBJECT_DECLARE_SIMPLE_TYPE(SiFiveEAONState, SIFIVE_E_AON)
diff --git a/include/hw/misc/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
index 6aa949e910d..adf9bd6da7e 100644
--- a/include/hw/misc/sifive_e_prci.h
+++ b/include/hw/misc/sifive_e_prci.h
@@ -20,6 +20,7 @@
 #define HW_SIFIVE_E_PRCI_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 enum {
     SIFIVE_E_PRCI_HFROSCCFG = 0x0,
diff --git a/include/hw/misc/sifive_test.h b/include/hw/misc/sifive_test.h
index 88a38d00c59..a995b397f66 100644
--- a/include/hw/misc/sifive_test.h
+++ b/include/hw/misc/sifive_test.h
@@ -21,6 +21,7 @@
 
 #include "hw/sysbus.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_SIFIVE_TEST "riscv.sifive.test"
 
diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
index 170d2148f25..99e9c0b6bcf 100644
--- a/include/hw/misc/sifive_u_otp.h
+++ b/include/hw/misc/sifive_u_otp.h
@@ -20,6 +20,7 @@
 #define HW_SIFIVE_U_OTP_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define SIFIVE_U_OTP_PA         0x00
 #define SIFIVE_U_OTP_PAIO       0x04
diff --git a/include/hw/misc/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
index 4d2491ad46d..07dce36055b 100644
--- a/include/hw/misc/sifive_u_prci.h
+++ b/include/hw/misc/sifive_u_prci.h
@@ -20,6 +20,7 @@
 #define HW_SIFIVE_U_PRCI_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define SIFIVE_U_PRCI_HFXOSCCFG     0x00
 #define SIFIVE_U_PRCI_COREPLLCFG0   0x04
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index e63941f18fc..5057ec42032 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -31,6 +31,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(CadenceGEMState, CADENCE_GEM)
 
 #include "net/net.h"
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define CADENCE_GEM_MAXREG        (0x00000800 / 4) /* Last valid GEM address */
 
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 609473d07b4..39fc92c9d69 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -26,6 +26,7 @@
 #include "hw/ssi/ibex_spi_host.h"
 #include "hw/boards.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
 OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index 539fe1156de..7bed56be91c 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -22,6 +22,7 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/boards.h"
 #include "hw/char/shakti_uart.h"
+#include "system/memory.h"
 
 #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
 #define RISCV_SHAKTI_SOC(obj) \
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 31180a680e6..3f547b0acdc 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -24,6 +24,7 @@
 #include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_e_aon.h"
 #include "hw/boards.h"
+#include "system/memory.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
 #define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/xiangshan_kmh.h b/include/hw/riscv/xiangshan_kmh.h
index c5dc6b1a9a7..5c7bc3a06ee 100644
--- a/include/hw/riscv/xiangshan_kmh.h
+++ b/include/hw/riscv/xiangshan_kmh.h
@@ -12,6 +12,7 @@
 
 #include "hw/boards.h"
 #include "hw/riscv/riscv_hart.h"
+#include "system/memory.h"
 
 #define XIANGSHAN_KMH_MAX_CPUS 16
 
diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
index 162be338636..357fbea4203 100644
--- a/include/hw/rtc/goldfish_rtc.h
+++ b/include/hw/rtc/goldfish_rtc.h
@@ -24,6 +24,7 @@
 
 #include "hw/sysbus.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_GOLDFISH_RTC "goldfish_rtc"
 OBJECT_DECLARE_SIMPLE_TYPE(GoldfishRTCState, GOLDFISH_RTC)
diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h
index 5bd5557b9a1..d2abeb916e2 100644
--- a/include/hw/ssi/ibex_spi_host.h
+++ b/include/hw/ssi/ibex_spi_host.h
@@ -32,6 +32,7 @@
 #include "qemu/fifo8.h"
 #include "qom/object.h"
 #include "qemu/timer.h"
+#include "system/memory.h"
 
 #define TYPE_IBEX_SPI_HOST "ibex-spi"
 #define IBEX_SPI_HOST(obj) \
diff --git a/include/hw/ssi/sifive_spi.h b/include/hw/ssi/sifive_spi.h
index d0c40cdb11b..0b1bc86e540 100644
--- a/include/hw/ssi/sifive_spi.h
+++ b/include/hw/ssi/sifive_spi.h
@@ -24,6 +24,7 @@
 
 #include "qemu/fifo8.h"
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define SIFIVE_SPI_REG_NUM  (0x78 / 4)
 
diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
index e1251383f2a..0640bc54ca0 100644
--- a/include/hw/timer/cadence_ttc.h
+++ b/include/hw/timer/cadence_ttc.h
@@ -20,6 +20,7 @@
 
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
+#include "system/memory.h"
 
 typedef struct {
     QEMUTimer *timer;
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index 41f5c82a920..9e58079e391 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -26,6 +26,7 @@
 #define HW_IBEX_TIMER_H
 
 #include "hw/sysbus.h"
+#include "system/memory.h"
 
 #define TYPE_IBEX_TIMER "ibex-timer"
 OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
diff --git a/include/hw/timer/sifive_pwm.h b/include/hw/timer/sifive_pwm.h
index 6a8cf7b29e4..bc68cca8efc 100644
--- a/include/hw/timer/sifive_pwm.h
+++ b/include/hw/timer/sifive_pwm.h
@@ -30,6 +30,7 @@
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "qom/object.h"
+#include "system/memory.h"
 
 #define TYPE_SIFIVE_PWM "sifive-pwm"
 
-- 
2.51.0