On 10/24/2025 2:56 PM, Zhao Liu wrote:
> - Move ARCH_LBR_NR_ENTRIES macro and LBREntry definition before XSAVE
> areas definitions.
personally, I prefer not moving them. Putting them together is friendly
and convenient when reading the code rather than bouncing through
different parts.
But considering the existing cases of BNDReg and BNDCSReg, I'm fine with
the movement.
> - Reorder XSavesArchLBR (area 15) between XSavePKRU (area 9) and
> XSaveXTILECFG (area 17), and reorder the related QEMU_BUILD_BUG_ON
> check to keep the same ordering.
This reorder is good.
> This makes xsave structures to be organized together and makes them
> clearer.
>
> Tested-by: Farrah Chen <farrah.chen@intel.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> target/i386/cpu.h | 38 +++++++++++++++++++-------------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 886a941e481c..ac527971d8cd 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1652,6 +1652,14 @@ typedef struct {
>
> #define NB_OPMASK_REGS 8
>
> +typedef struct {
> + uint64_t from;
> + uint64_t to;
> + uint64_t info;
> +} LBREntry;
> +
> +#define ARCH_LBR_NR_ENTRIES 32
> +
> /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
> * that APIC ID hasn't been set yet
> */
> @@ -1729,24 +1737,6 @@ typedef struct XSavePKRU {
> uint32_t padding;
> } XSavePKRU;
>
> -/* Ext. save area 17: AMX XTILECFG state */
> -typedef struct XSaveXTILECFG {
> - uint8_t xtilecfg[64];
> -} XSaveXTILECFG;
> -
> -/* Ext. save area 18: AMX XTILEDATA state */
> -typedef struct XSaveXTILEDATA {
> - uint8_t xtiledata[8][1024];
> -} XSaveXTILEDATA;
> -
> -typedef struct {
> - uint64_t from;
> - uint64_t to;
> - uint64_t info;
> -} LBREntry;
> -
> -#define ARCH_LBR_NR_ENTRIES 32
> -
> /* Ext. save area 15: Arch LBR state */
> typedef struct XSaveArchLBR {
> uint64_t lbr_ctl;
> @@ -1757,6 +1747,16 @@ typedef struct XSaveArchLBR {
> LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
> } XSaveArchLBR;
>
> +/* Ext. save area 17: AMX XTILECFG state */
> +typedef struct XSaveXTILECFG {
> + uint8_t xtilecfg[64];
> +} XSaveXTILECFG;
> +
> +/* Ext. save area 18: AMX XTILEDATA state */
> +typedef struct XSaveXTILEDATA {
> + uint8_t xtiledata[8][1024];
> +} XSaveXTILEDATA;
> +
> QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
> QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
> QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
> @@ -1764,9 +1764,9 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
> QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
> QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
> QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
> +QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) != 0x328);
> QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
> QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
> -QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) != 0x328);
>
> typedef struct ExtSaveArea {
> uint32_t feature, bits;