On Tue, Oct 28, 2025 at 04:29:58PM +0800, Xiaoyao Li wrote:
> Date: Tue, 28 Oct 2025 16:29:58 +0800
> From: Xiaoyao Li <xiaoyao.li@intel.com>
> Subject: Re: [PATCH v3 15/20] i386/machine: Add vmstate for cet-ss and
> cet-ibt
>
> On 10/24/2025 2:56 PM, Zhao Liu wrote:
> > From: Yang Weijiang <weijiang.yang@intel.com>
> >
> > Add vmstates for cet-ss and cet-ibt
> >
> > Tested-by: Farrah Chen <farrah.chen@intel.com>
> > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> > Co-developed-by: Chao Gao <chao.gao@intel.com>
> > Signed-off-by: Chao Gao <chao.gao@intel.com>
> > Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > ---
> > Changes Since v2:
> > - Split a subsection "vmstate_ss" since shstk is user-configurable.
> > ---
> > target/i386/machine.c | 53 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 53 insertions(+)
> >
> > diff --git a/target/i386/machine.c b/target/i386/machine.c
> > index 45b7cea80aa7..3ad07ec82428 100644
> > --- a/target/i386/machine.c
> > +++ b/target/i386/machine.c
> > @@ -1668,6 +1668,58 @@ static const VMStateDescription vmstate_triple_fault = {
> > }
> > };
> > +static bool shstk_needed(void *opaque)
> > +{
> > + X86CPU *cpu = opaque;
> > + CPUX86State *env = &cpu->env;
> > +
> > + return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK);
> > +}
> > +
> > +static const VMStateDescription vmstate_ss = {
> > + .name = "cpu/cet_ss",
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .needed = shstk_needed,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_UINT64(env.pl0_ssp, X86CPU),
> > + VMSTATE_UINT64(env.pl1_ssp, X86CPU),
> > + VMSTATE_UINT64(env.pl2_ssp, X86CPU),
> > + VMSTATE_UINT64(env.pl3_ssp, X86CPU),
> > +#ifdef TARGET_X86_64
> > + /* This MSR is only present on Intel 64 architecture. */
> > + VMSTATE_UINT64(env.int_ssp_table, X86CPU),
> > +#endif
>
> It seems we need to split int_ssp_table into a separate vmstate_*
>
> Its .needed function needs to check both CPUID_7_0_ECX_CET_SHSTK &&
> CPUID_EXT2_LM.
Ok, will split this entry into a subsection. Thanks.
> > + VMSTATE_UINT64(env.guest_ssp, X86CPU),
> > + VMSTATE_END_OF_LIST()
> > + }
> > +};
> > +
> > +static bool cet_needed(void *opaque)
> > +{
> > + X86CPU *cpu = opaque;
> > + CPUX86State *env = &cpu->env;
> > +
> > + return !!((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) ||
> > + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT));
> > +}
> > +
> > +static const VMStateDescription vmstate_cet = {
> > + .name = "cpu/cet",
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .needed = cet_needed,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_UINT64(env.u_cet, X86CPU),
> > + VMSTATE_UINT64(env.s_cet, X86CPU),
> > + VMSTATE_END_OF_LIST()
> > + },
> > + .subsections = (const VMStateDescription * const []) {
> > + &vmstate_ss,
here: ^^^^^^^^^^^^^
> > + NULL,
> > + },
> > +};
> > +
> > const VMStateDescription vmstate_x86_cpu = {
> > .name = "cpu",
> > .version_id = 12,
> > @@ -1817,6 +1869,7 @@ const VMStateDescription vmstate_x86_cpu = {
> > #endif
> > &vmstate_arch_lbr,
> > &vmstate_triple_fault,
> > + &vmstate_cet,
>
> missing &vmstate_ss
I made vmstate_ss as a subsection in vmstate_cet
Regards,
Zhao