On 10/24/2025 2:56 PM, Zhao Liu wrote:
> From: Yang Weijiang <weijiang.yang@intel.com>
>
> CET provides a new architectural register, shadow stack pointer (SSP),
> which cannot be directly encoded as a source, destination or memory
> operand in instructions. But Intel VMCS & VMCB provide fields to
> save/load guest & host's ssp.
>
> It's necessary to save & load Guest's ssp before & after migration. To
> support this, KVM implements Guest's SSP as a special KVM internal
> register - KVM_REG_GUEST_SSP, and allows QEMU to save & load it via
> KVM_GET_ONE_REG/KVM_SET_ONE_REG.
>
> Cache KVM_REG_GUEST_SSP in X86CPUState.
>
> Tested-by: Farrah Chen <farrah.chen@intel.com>
> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> Co-developed-by: Chao Gao <chao.gao@intel.com>
> Signed-off-by: Chao Gao <chao.gao@intel.com>
> Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> target/i386/cpu.h | 1 +
> target/i386/kvm/kvm.c | 39 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 4edb977575e2..ad4287822831 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2105,6 +2105,7 @@ typedef struct CPUArchState {
> uint64_t pl2_ssp;
> uint64_t pl3_ssp;
> uint64_t int_ssp_table;
> + uint64_t guest_ssp;
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index 92c2fd6d6aee..412e99ba5b53 100644
> --- a/target/i386/kvm/kvm.c
> +++ b/target/i386/kvm/kvm.c
> @@ -4280,6 +4280,35 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level)
> return kvm_buf_set_msrs(cpu);
> }
>
> +static int kvm_put_kvm_regs(X86CPU *cpu)
> +{
> + CPUX86State *env = &cpu->env;
> + int ret;
> +
> + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) {
> + ret = kvm_set_one_reg(CPU(cpu), KVM_X86_REG_KVM(KVM_REG_GUEST_SSP),
> + &env->guest_ssp);
> + if (ret) {
> + return ret;
> + }
> + }
> + return 0;
> +}
> +
> +static int kvm_get_kvm_regs(X86CPU *cpu)
> +{
> + CPUX86State *env = &cpu->env;
> + int ret;
> +
> + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) {
> + ret = kvm_get_one_reg(CPU(cpu), KVM_X86_REG_KVM(KVM_REG_GUEST_SSP),
> + &env->guest_ssp);
> + if (ret) {
> + return ret;
> + }
> + }
> + return 0;
> +}
>
> static int kvm_get_xsave(X86CPU *cpu)
> {
> @@ -5425,6 +5454,11 @@ int kvm_arch_put_registers(CPUState *cpu, KvmPutState level, Error **errp)
> error_setg_errno(errp, -ret, "Failed to set MSRs");
> return ret;
> }
> + ret = kvm_put_kvm_regs(x86_cpu);
> + if (ret < 0) {
> + error_setg_errno(errp, -ret, "Failed to set KVM type registers");
> + return ret;
> + }
> ret = kvm_put_vcpu_events(x86_cpu, level);
> if (ret < 0) {
> error_setg_errno(errp, -ret, "Failed to set vCPU events");
> @@ -5497,6 +5531,11 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)
> error_setg_errno(errp, -ret, "Failed to get MSRs");
> goto out;
> }
> + ret = kvm_get_kvm_regs(cpu);
> + if (ret < 0) {
> + error_setg_errno(errp, -ret, "Failed to get KVM type registers");
> + goto out;
> + }
> ret = kvm_get_apic(cpu);
> if (ret < 0) {
> error_setg_errno(errp, -ret, "Failed to get APIC");