On Fri, Oct 24, 2025 at 9:49 AM <alistair23@gmail.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 88b1716a407459c8189473e4667653cb8e4c3df7:
>
> Merge tag 'pull-target-arm-20251023' of https://gitlab.com/pm215/qemu into staging (2025-10-23 13:17:27 -0500)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251024
>
> for you to fetch changes up to eccf20c02a5ad913a910444dc6bbe5de0952d254:
>
> target/riscv: Make PMP CSRs conform to WARL constraints (2025-10-24 09:24:08 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for 10.2
>
> * Correct mmu-type property of sifive_u harts in device tree
> * Centralize MO_TE uses in a pair of helpers
> * Fix Ethernet interface support for microchip-icicle-kit
> * Fix mask for smsiaddrcfgh
> * Fix env->priv setting in reset_regs_csr()
> * Coverity-related fixes
> * Fix riscv_cpu_sirq_pending() mask
> * Fix a uninitialized variable warning
> * Make PMP granularity configurable
I have dropped the MIP Boston board as that seems to fail when running
on s390 [1]. Hopefully this passes CI, but I'm unable to check that it
works on s390
1: https://gitlab.com/qemu-project/qemu/-/jobs/11827080939#L5859
Alistair
>
> ----------------------------------------------------------------
> Akihiko Odaki (1):
> target/riscv: Fix a uninitialized variable warning
>
> Daniel Henrique Barboza (3):
> target/riscv/kvm: fix env->priv setting in reset_regs_csr()
> target/riscv/riscv-qmp-cmds.c: coverity-related fixes
> target/riscv: fix riscv_cpu_sirq_pending() mask
>
> Djordje Todorovic (1):
> hw/intc: Allow gaps in hartids for aclint and aplic
>
> Guenter Roeck (4):
> hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
> hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
> hw/net/cadence_gem: Add pcs-enabled property
> microchip icicle: Enable PCS on Cadence Ethernet
>
> Jay Chang (2):
> target/riscv: Make PMP granularity configurable
> target/riscv: Make PMP CSRs conform to WARL constraints
>
> Jialong Yang (1):
> aplic: fix mask for smsiaddrcfgh
>
> Philippe Mathieu-Daudé (12):
> target/riscv: Explode MO_TExx -> MO_TE | MO_xx
> target/riscv: Conceal MO_TE within gen_amo()
> target/riscv: Conceal MO_TE within gen_inc()
> target/riscv: Conceal MO_TE within gen_load() / gen_store()
> target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()
> target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()
> target/riscv: Conceal MO_TE within gen_storepair_tl()
> target/riscv: Conceal MO_TE within gen_cmpxchg*()
> target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()
> target/riscv: Factor MemOp variable out when MO_TE is set
> target/riscv: Introduce mo_endian() helper
> target/riscv: Introduce mo_endian_env() helper
>
> Zejun Zhao (1):
> hw/riscv: Correct mmu-type property of sifive_u harts in device tree
>
> include/hw/net/cadence_gem.h | 4 ++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> hw/intc/riscv_aclint.c | 18 ++++-
> hw/intc/riscv_aplic.c | 42 ++++++++----
> hw/net/cadence_gem.c | 31 +++++++--
> hw/riscv/microchip_pfsoc.c | 6 ++
> hw/riscv/sifive_u.c | 2 +-
> target/riscv/cpu.c | 39 +++++++++++
> target/riscv/cpu_helper.c | 3 +-
> target/riscv/kvm/kvm-cpu.c | 1 +
> target/riscv/op_helper.c | 30 +++++---
> target/riscv/pmp.c | 46 +++++++++++++
> target/riscv/riscv-qmp-cmds.c | 22 +++---
> target/riscv/tcg/tcg-cpu.c | 12 ++--
> target/riscv/translate.c | 16 ++++-
> target/riscv/insn_trans/trans_rva.c.inc | 50 ++++++++------
> target/riscv/insn_trans/trans_rvd.c.inc | 6 +-
> target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
> target/riscv/insn_trans/trans_rvi.c.inc | 24 ++++---
> target/riscv/insn_trans/trans_rvzabha.c.inc | 20 +++---
> target/riscv/insn_trans/trans_rvzacas.c.inc | 12 ++--
> target/riscv/insn_trans/trans_rvzce.c.inc | 12 ++--
> target/riscv/insn_trans/trans_rvzfh.c.inc | 8 ++-
> target/riscv/insn_trans/trans_rvzicfiss.c.inc | 10 +--
> target/riscv/insn_trans/trans_xthead.c.inc | 98 +++++++++++++++------------
> 26 files changed, 361 insertions(+), 159 deletions(-)