From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c0e80879c876cbe4cbde43a92403329bcedf2ba0:

  Merge tag 'pull-vfio-20251022' of https://github.com/legoater/qemu into staging (2025-10-22 08:01:21 -0500)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251023

for you to fetch changes up to 741566c3e07fd34ed28d4464d1d7fda67db12925:

  target/riscv: Make PMP CSRs conform to WARL constraints (2025-10-23 14:11:45 +1000)

----------------------------------------------------------------
Second RISC-V PR for 10.2

* Correct mmu-type property of sifive_u harts in device tree
* Centralize MO_TE uses in a pair of helpers
* Fix Ethernet interface support for microchip-icicle-kit
* Fix mask for smsiaddrcfgh
* Add support for MIPS P8700 CPU
* Fix env->priv setting in reset_regs_csr()
* Coverity-related fixes
* Fix riscv_cpu_sirq_pending() mask
* Fix a uninitialized variable warning
* Make PMP granularity configurable

----------------------------------------------------------------
Akihiko Odaki (1):
      target/riscv: Fix a uninitialized variable warning

Daniel Henrique Barboza (3):
      target/riscv/kvm: fix env->priv setting in reset_regs_csr()
      target/riscv/riscv-qmp-cmds.c: coverity-related fixes
      target/riscv: fix riscv_cpu_sirq_pending() mask

Djordje Todorovic (13):
      hw/intc: Allow gaps in hartids for aclint and aplic
      target/riscv: Add cpu_set_exception_base
      target/riscv: Add MIPS P8700 CPU
      target/riscv: Add MIPS P8700 CSRs
      target/riscv: Add mips.ccmov instruction
      target/riscv: Add mips.pref instruction
      target/riscv: Add Xmipslsp instructions
      hw/misc: Add RISC-V CMGCR device implementation
      hw/misc: Add RISC-V CPC device implementation
      hw/riscv: Add support for RISCV CPS
      hw/riscv: Add support for MIPS Boston-aia board mode
      riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
      test/functional: Add test for boston-aia board

Guenter Roeck (4):
      hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
      hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
      hw/net/cadence_gem: Add pcs-enabled property
      microchip icicle: Enable PCS on Cadence Ethernet

Jay Chang (2):
      target/riscv: Make PMP granularity configurable
      target/riscv: Make PMP CSRs conform to WARL constraints

Jialong Yang (1):
      aplic: fix mask for smsiaddrcfgh

Philippe Mathieu-Daudé (12):
      target/riscv: Explode MO_TExx -> MO_TE | MO_xx
      target/riscv: Conceal MO_TE within gen_amo()
      target/riscv: Conceal MO_TE within gen_inc()
      target/riscv: Conceal MO_TE within gen_load() / gen_store()
      target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()
      target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()
      target/riscv: Conceal MO_TE within gen_storepair_tl()
      target/riscv: Conceal MO_TE within gen_cmpxchg*()
      target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()
      target/riscv: Factor MemOp variable out when MO_TE is set
      target/riscv: Introduce mo_endian() helper
      target/riscv: Introduce mo_endian_env() helper

Zejun Zhao (1):
      hw/riscv: Correct mmu-type property of sifive_u harts in device tree

 docs/system/riscv/mips.rst                    |  20 ++
 docs/system/target-riscv.rst                  |   1 +
 configs/devices/riscv64-softmmu/default.mak   |   1 +
 include/hw/misc/riscv_cmgcr.h                 |  50 +++
 include/hw/misc/riscv_cpc.h                   |  64 ++++
 include/hw/net/cadence_gem.h                  |   4 +
 include/hw/riscv/cps.h                        |  66 ++++
 target/riscv/cpu-qom.h                        |   1 +
 target/riscv/cpu.h                            |   8 +
 target/riscv/cpu_cfg.h                        |   5 +
 target/riscv/cpu_vendorid.h                   |   1 +
 target/riscv/cpu_cfg_fields.h.inc             |   4 +
 target/riscv/xmips.decode                     |  35 ++
 hw/intc/riscv_aclint.c                        |  18 +-
 hw/intc/riscv_aplic.c                         |  42 ++-
 hw/misc/riscv_cmgcr.c                         | 248 ++++++++++++++
 hw/misc/riscv_cpc.c                           | 265 ++++++++++++++
 hw/net/cadence_gem.c                          |  31 +-
 hw/riscv/boston-aia.c                         | 476 ++++++++++++++++++++++++++
 hw/riscv/cps.c                                | 196 +++++++++++
 hw/riscv/microchip_pfsoc.c                    |   6 +
 hw/riscv/sifive_u.c                           |   2 +-
 target/riscv/cpu.c                            |  83 +++++
 target/riscv/cpu_helper.c                     |   3 +-
 target/riscv/kvm/kvm-cpu.c                    |   1 +
 target/riscv/mips_csr.c                       | 217 ++++++++++++
 target/riscv/op_helper.c                      |  30 +-
 target/riscv/pmp.c                            |  46 +++
 target/riscv/riscv-qmp-cmds.c                 |  22 +-
 target/riscv/tcg/tcg-cpu.c                    |  12 +-
 target/riscv/translate.c                      |  19 +-
 target/riscv/insn_trans/trans_rva.c.inc       |  50 +--
 target/riscv/insn_trans/trans_rvd.c.inc       |   6 +-
 target/riscv/insn_trans/trans_rvf.c.inc       |   6 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |  24 +-
 target/riscv/insn_trans/trans_rvzabha.c.inc   |  20 +-
 target/riscv/insn_trans/trans_rvzacas.c.inc   |  12 +-
 target/riscv/insn_trans/trans_rvzce.c.inc     |  12 +-
 target/riscv/insn_trans/trans_rvzfh.c.inc     |   8 +-
 target/riscv/insn_trans/trans_rvzicfiss.c.inc |  10 +-
 target/riscv/insn_trans/trans_xmips.c.inc     | 136 ++++++++
 target/riscv/insn_trans/trans_xthead.c.inc    |  98 +++---
 hw/misc/Kconfig                               |  17 +
 hw/misc/meson.build                           |   3 +
 hw/riscv/Kconfig                              |   6 +
 hw/riscv/meson.build                          |   3 +
 target/riscv/meson.build                      |   2 +
 tests/functional/riscv64/meson.build          |   2 +
 tests/functional/riscv64/test_boston.py       | 123 +++++++
 49 files changed, 2356 insertions(+), 159 deletions(-)
 create mode 100644 docs/system/riscv/mips.rst
 create mode 100644 include/hw/misc/riscv_cmgcr.h
 create mode 100644 include/hw/misc/riscv_cpc.h
 create mode 100644 include/hw/riscv/cps.h
 create mode 100644 target/riscv/xmips.decode
 create mode 100644 hw/misc/riscv_cmgcr.c
 create mode 100644 hw/misc/riscv_cpc.c
 create mode 100644 hw/riscv/boston-aia.c
 create mode 100644 hw/riscv/cps.c
 create mode 100644 target/riscv/mips_csr.c
 create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
 create mode 100755 tests/functional/riscv64/test_boston.py

On 10/22/25 23:13, alistair23@gmail.com wrote:
> From: Alistair Francis<alistair.francis@wdc.com>
> 
> The following changes since commit c0e80879c876cbe4cbde43a92403329bcedf2ba0:
> 
>    Merge tag 'pull-vfio-20251022' ofhttps://github.com/legoater/qemu into staging (2025-10-22 08:01:21 -0500)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251023
> 
> for you to fetch changes up to 741566c3e07fd34ed28d4464d1d7fda67db12925:
> 
>    target/riscv: Make PMP CSRs conform to WARL constraints (2025-10-23 14:11:45 +1000)
> 
> ----------------------------------------------------------------
> Second RISC-V PR for 10.2
> 
> * Correct mmu-type property of sifive_u harts in device tree
> * Centralize MO_TE uses in a pair of helpers
> * Fix Ethernet interface support for microchip-icicle-kit
> * Fix mask for smsiaddrcfgh
> * Add support for MIPS P8700 CPU
> * Fix env->priv setting in reset_regs_csr()
> * Coverity-related fixes
> * Fix riscv_cpu_sirq_pending() mask
> * Fix a uninitialized variable warning
> * Make PMP granularity configurable

Something in here is causing failures on s390x:

https://gitlab.com/qemu-project/qemu/-/jobs/11827080939#L5859

It seems obvious to suspect the endianness changes from the big-endian host, but I also 
don't immediately see anything wrong.


r~

On Fri, Oct 24, 2025 at 4:15 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/22/25 23:13, alistair23@gmail.com wrote:
> > From: Alistair Francis<alistair.francis@wdc.com>
> >
> > The following changes since commit c0e80879c876cbe4cbde43a92403329bcedf2ba0:
> >
> >    Merge tag 'pull-vfio-20251022' ofhttps://github.com/legoater/qemu into staging (2025-10-22 08:01:21 -0500)
> >
> > are available in the Git repository at:
> >
> >    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251023
> >
> > for you to fetch changes up to 741566c3e07fd34ed28d4464d1d7fda67db12925:
> >
> >    target/riscv: Make PMP CSRs conform to WARL constraints (2025-10-23 14:11:45 +1000)
> >
> > ----------------------------------------------------------------
> > Second RISC-V PR for 10.2
> >
> > * Correct mmu-type property of sifive_u harts in device tree
> > * Centralize MO_TE uses in a pair of helpers
> > * Fix Ethernet interface support for microchip-icicle-kit
> > * Fix mask for smsiaddrcfgh
> > * Add support for MIPS P8700 CPU
> > * Fix env->priv setting in reset_regs_csr()
> > * Coverity-related fixes
> > * Fix riscv_cpu_sirq_pending() mask
> > * Fix a uninitialized variable warning
> > * Make PMP granularity configurable
>
> Something in here is causing failures on s390x:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/11827080939#L5859
>
> It seems obvious to suspect the endianness changes from the big-endian host, but I also
> don't immediately see anything wrong.

It seem like only the new Boston machine is failing, so I think that's
the issue.

Alistair

>
>
> r~