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[PATCH] target/riscv: fix riscv_cpu_sirq_pending() mask

Daniel Henrique Barboza posted 1 patch 3 weeks, 2 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251022124340.493358-1-dbarboza@ventanamicro.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
[PATCH] target/riscv: fix riscv_cpu_sirq_pending() mask
Posted by Daniel Henrique Barboza 3 weeks, 2 days ago 
We're filtering out (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) from S-mode
pending interrupts without apparent reason. There's no special treatment
for these ints as far as the spec goes, and this filtering is causing
read_stopi() to miss those VS interrupts [1].

We shouldn't return delegated VS interrupts in S-mode though, so change
the current mask with "~env->hideleg". Note that this is the same
handling we're doing in riscv_cpu_mirq_pending() and env->mideleg.

[1] https://gitlab.com/qemu-project/qemu/-/issues/2820

Closes: https://gitlab.com/qemu-project/qemu/-/issues/2820
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3479a62cc7..360db133e2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -443,8 +443,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
 
 int riscv_cpu_sirq_pending(CPURISCVState *env)
 {
-    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
-                    ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
+    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
     uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
 
     return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
-- 
2.51.0
Re: [PATCH] target/riscv: fix riscv_cpu_sirq_pending() mask
Posted by Alistair Francis 3 weeks, 1 day ago 
On Wed, Oct 22, 2025 at 10:45 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We're filtering out (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) from S-mode
> pending interrupts without apparent reason. There's no special treatment
> for these ints as far as the spec goes, and this filtering is causing
> read_stopi() to miss those VS interrupts [1].
>
> We shouldn't return delegated VS interrupts in S-mode though, so change
> the current mask with "~env->hideleg". Note that this is the same
> handling we're doing in riscv_cpu_mirq_pending() and env->mideleg.
>
> [1] https://gitlab.com/qemu-project/qemu/-/issues/2820
>
> Closes: https://gitlab.com/qemu-project/qemu/-/issues/2820
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu_helper.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 3479a62cc7..360db133e2 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -443,8 +443,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
>
>  int riscv_cpu_sirq_pending(CPURISCVState *env)
>  {
> -    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
> -                    ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
> +    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
>      uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
>
>      return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
> --
> 2.51.0
>
>
Re: [PATCH] target/riscv: fix riscv_cpu_sirq_pending() mask
Posted by Alistair Francis 3 weeks, 1 day ago 
On Wed, Oct 22, 2025 at 10:45 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We're filtering out (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) from S-mode
> pending interrupts without apparent reason. There's no special treatment
> for these ints as far as the spec goes, and this filtering is causing
> read_stopi() to miss those VS interrupts [1].
>
> We shouldn't return delegated VS interrupts in S-mode though, so change
> the current mask with "~env->hideleg". Note that this is the same
> handling we're doing in riscv_cpu_mirq_pending() and env->mideleg.
>
> [1] https://gitlab.com/qemu-project/qemu/-/issues/2820
>
> Closes: https://gitlab.com/qemu-project/qemu/-/issues/2820
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 3479a62cc7..360db133e2 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -443,8 +443,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
>
>  int riscv_cpu_sirq_pending(CPURISCVState *env)
>  {
> -    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg &
> -                    ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
> +    uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
>      uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
>
>      return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
> --
> 2.51.0
>
>

Patchew 2.1-devel-b67e4c2

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