[PATCH v2 0/2] Make PMP granularity configurable

Jay Chang posted 2 patches 3 weeks, 2 days ago
Only 0 patches received!
There is a newer version of this series
target/riscv/cpu.c                | 39 ++++++++++++++++++++++++++
target/riscv/cpu.h                |  1 +
target/riscv/cpu_cfg_fields.h.inc |  1 +
target/riscv/pmp.c                | 46 +++++++++++++++++++++++++++++++
4 files changed, 87 insertions(+)
[PATCH v2 0/2] Make PMP granularity configurable
Posted by Jay Chang 3 weeks, 2 days ago
This patch series enhances QEMU's RISC-V PMP support to conform with
the RISC-V Privileged Specification regarding PMP granularity and WARL
constraints.

Previously, QEMU always used a fixed minimum PMP granularity of 4 bytes.
This series introduces a configurable "pmp-granularity" parameter, allowing
platforms to specify larger granularity values. In addition, the handling of
pmpcfg and pmpaddr CSRs has been updated to follow WARL constraints. For
example, when NA4 is not valid due to a larger granularity, it is silently
ignored. TOR and NAPOT address ranges are also properly aligned according to
the configured granularity.

A new CPU parameter `pmp-granularity` is now available on the QEMU command
line. For example:

    -cpu rv64,g=true,c=true,pmp=true,pmp-granularity=1024

If not provided, the default remains 4 bytes.

---

Patch summary:

1. target/riscv: Make PMP granularity configurable
   - Introduce CPU property `pmp-granularity` for platforms to configure
     PMP granularity.
   - Default remains 4 bytes if unspecified.

2. target/riscv: Make PMP CSRs conform to WARL constraints
   - Update pmpcfg and pmpaddr handling to follow WARL semantics.
   - Align start and end addresses of TOR regions to PMP granularity.
   - Ensure software can read back correct values per the spec.

PATCH v2 update
Change UL type to ULL to prevent bit-width errors.

Jay Chang (2):
  target/riscv: Make PMP granularity configurable
  target/riscv: Make PMP CSRs conform to WARL constraints

 target/riscv/cpu.c                | 39 ++++++++++++++++++++++++++
 target/riscv/cpu.h                |  1 +
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 target/riscv/pmp.c                | 46 +++++++++++++++++++++++++++++++
 4 files changed, 87 insertions(+)

-- 
2.48.1
Re: [PATCH v2 0/2] Make PMP granularity configurable
Posted by Jay Chang 3 weeks, 2 days ago
Sorry for the error version,  please ignore it.

Thanks & Regards

On Wed, Oct 22, 2025 at 10:26 AM Jay Chang <jay.chang@sifive.com> wrote:

> This patch series enhances QEMU's RISC-V PMP support to conform with
> the RISC-V Privileged Specification regarding PMP granularity and WARL
> constraints.
>
> Previously, QEMU always used a fixed minimum PMP granularity of 4 bytes.
> This series introduces a configurable "pmp-granularity" parameter, allowing
> platforms to specify larger granularity values. In addition, the handling
> of
> pmpcfg and pmpaddr CSRs has been updated to follow WARL constraints. For
> example, when NA4 is not valid due to a larger granularity, it is silently
> ignored. TOR and NAPOT address ranges are also properly aligned according
> to
> the configured granularity.
>
> A new CPU parameter `pmp-granularity` is now available on the QEMU command
> line. For example:
>
>     -cpu rv64,g=true,c=true,pmp=true,pmp-granularity=1024
>
> If not provided, the default remains 4 bytes.
>
> ---
>
> Patch summary:
>
> 1. target/riscv: Make PMP granularity configurable
>    - Introduce CPU property `pmp-granularity` for platforms to configure
>      PMP granularity.
>    - Default remains 4 bytes if unspecified.
>
> 2. target/riscv: Make PMP CSRs conform to WARL constraints
>    - Update pmpcfg and pmpaddr handling to follow WARL semantics.
>    - Align start and end addresses of TOR regions to PMP granularity.
>    - Ensure software can read back correct values per the spec.
>
> PATCH v2 update
> Change UL type to ULL to prevent bit-width errors.
>
> Jay Chang (2):
>   target/riscv: Make PMP granularity configurable
>   target/riscv: Make PMP CSRs conform to WARL constraints
>
>  target/riscv/cpu.c                | 39 ++++++++++++++++++++++++++
>  target/riscv/cpu.h                |  1 +
>  target/riscv/cpu_cfg_fields.h.inc |  1 +
>  target/riscv/pmp.c                | 46 +++++++++++++++++++++++++++++++
>  4 files changed, 87 insertions(+)
>
> --
> 2.48.1
>
>