hw/riscv: adding support for NeoRV32 RiscV MCU

[PATCH v1 0/1] hw/riscv: adding support for NeoRV32 RiscV MCU

Michael Levit posted 1 patch 3 weeks, 3 days ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251020181435.8242-1-michael@videogpu.com

Maintainers: Paolo Bonzini <pbonzini@redhat.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

.gitignore                                  |   1 +
configs/devices/riscv32-softmmu/default.mak |   1 +
docs/system/riscv/neorv32.rst               | 110 +++++
hw/char/Kconfig                             |   3 +
hw/char/meson.build                         |   1 +
hw/char/neorv32_uart.c                      | 311 ++++++++++++
hw/misc/Kconfig                             |   2 +
hw/misc/meson.build                         |   1 +
hw/misc/neorv32_sysinfo.c                   | 183 +++++++
hw/misc/neorv32_sysinfo.h                   |  79 +++
hw/misc/neorv32_sysinfo_rtl.h               | 134 ++++++
hw/riscv/Kconfig                            |   8 +
hw/riscv/meson.build                        |   1 +
hw/riscv/neorv32.c                          | 219 +++++++++
hw/ssi/Kconfig                              |   4 +
hw/ssi/meson.build                          |   1 +
hw/ssi/neorv32_spi.c                        | 504 ++++++++++++++++++++
include/hw/char/neorv32_uart.h              |  68 +++
include/hw/riscv/neorv32.h                  |  60 +++
include/hw/ssi/neorv32_spi.h                |  70 +++
target/riscv/cpu-qom.h                      |   2 +
target/riscv/cpu.c                          |  18 +
target/riscv/cpu.h                          |   3 +
target/riscv/cpu_cfg.h                      |   1 +
target/riscv/cpu_cfg_fields.h.inc           |   1 +
target/riscv/cpu_vendorid.h                 |   2 +
target/riscv/meson.build                    |   1 +
target/riscv/neorv32_csr.c                  |  54 +++
28 files changed, 1843 insertions(+)
create mode 100644 docs/system/riscv/neorv32.rst
create mode 100644 hw/char/neorv32_uart.c
create mode 100644 hw/misc/neorv32_sysinfo.c
create mode 100644 hw/misc/neorv32_sysinfo.h
create mode 100644 hw/misc/neorv32_sysinfo_rtl.h
create mode 100644 hw/riscv/neorv32.c
create mode 100644 hw/ssi/neorv32_spi.c
create mode 100644 include/hw/char/neorv32_uart.h
create mode 100644 include/hw/riscv/neorv32.h
create mode 100644 include/hw/ssi/neorv32_spi.h
create mode 100644 target/riscv/neorv32_csr.c

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[PATCH v1 0/1] hw/riscv: adding support for NeoRV32 RiscV MCU

Posted by Michael Levit 3 weeks, 3 days ago

1) Initial support for Neorv32 soft-core MCU
2) IMEM, DMEM memory regions, bootloader ROM
3) Basic support for UART0, Basic support for SPI
4) Added SPI flash memory for loading firmware following  bootloader
5) Based on Neorv32 RTL implementation repo
   https://github.com/stnolting/neorv32 commit id 7d0ef6b2
Thanks in advance for review!

Michael (1):
  hw/riscv: adding support for NeoRV32 RiscV MCU

 .gitignore                                  |   1 +
 configs/devices/riscv32-softmmu/default.mak |   1 +
 docs/system/riscv/neorv32.rst               | 110 +++++
 hw/char/Kconfig                             |   3 +
 hw/char/meson.build                         |   1 +
 hw/char/neorv32_uart.c                      | 311 ++++++++++++
 hw/misc/Kconfig                             |   2 +
 hw/misc/meson.build                         |   1 +
 hw/misc/neorv32_sysinfo.c                   | 183 +++++++
 hw/misc/neorv32_sysinfo.h                   |  79 +++
 hw/misc/neorv32_sysinfo_rtl.h               | 134 ++++++
 hw/riscv/Kconfig                            |   8 +
 hw/riscv/meson.build                        |   1 +
 hw/riscv/neorv32.c                          | 219 +++++++++
 hw/ssi/Kconfig                              |   4 +
 hw/ssi/meson.build                          |   1 +
 hw/ssi/neorv32_spi.c                        | 504 ++++++++++++++++++++
 include/hw/char/neorv32_uart.h              |  68 +++
 include/hw/riscv/neorv32.h                  |  60 +++
 include/hw/ssi/neorv32_spi.h                |  70 +++
 target/riscv/cpu-qom.h                      |   2 +
 target/riscv/cpu.c                          |  18 +
 target/riscv/cpu.h                          |   3 +
 target/riscv/cpu_cfg.h                      |   1 +
 target/riscv/cpu_cfg_fields.h.inc           |   1 +
 target/riscv/cpu_vendorid.h                 |   2 +
 target/riscv/meson.build                    |   1 +
 target/riscv/neorv32_csr.c                  |  54 +++
 28 files changed, 1843 insertions(+)
 create mode 100644 docs/system/riscv/neorv32.rst
 create mode 100644 hw/char/neorv32_uart.c
 create mode 100644 hw/misc/neorv32_sysinfo.c
 create mode 100644 hw/misc/neorv32_sysinfo.h
 create mode 100644 hw/misc/neorv32_sysinfo_rtl.h
 create mode 100644 hw/riscv/neorv32.c
 create mode 100644 hw/ssi/neorv32_spi.c
 create mode 100644 include/hw/char/neorv32_uart.h
 create mode 100644 include/hw/riscv/neorv32.h
 create mode 100644 include/hw/ssi/neorv32_spi.h
 create mode 100644 target/riscv/neorv32_csr.c

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2.20.1