target/ppc/cpu-models.h | 4 -- target/ppc/cpu-models.c | 5 -- target/ppc/cpu_init.c | 147 +--------------------------------------- 3 files changed, 2 insertions(+), 154 deletions(-)
From: Thomas Huth <thuth@redhat.com>
There is currently no machine in QEMU (except the "none" machine)
that can be run with one of the e200 ppc CPUs - all machines either
complain about an invalid CPU type or crash QEMU immediatly.
Looking at the history of this CPU type, it seems like it has never
been used in QEMU and only implemented as a placeholder (see e.g. the
comment about unimplemented instructions in the POWERPC_FAMILY(e200)
section of cpu_init.c). Being completely unused and unusable since
such a long time, let's just remove it now.
Note: The init_excp_e200() is used by the e500 CPUs, too, so we
rename this function to init_excp_e500() instead of removing it.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
target/ppc/cpu-models.h | 4 --
target/ppc/cpu-models.c | 5 --
target/ppc/cpu_init.c | 147 +---------------------------------------
3 files changed, 2 insertions(+), 154 deletions(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index c6cd27f390e..a439eb37ee4 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -120,10 +120,6 @@ enum {
#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
- /* e200 family */
- /* e200 cores */
- CPU_POWERPC_e200z5 = 0x81000000,
- CPU_POWERPC_e200z6 = 0x81120000,
/* e300 family */
/* e300 cores */
CPU_POWERPC_e300c1 = 0x00830010,
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 89ae763c7f6..26b6debcfc9 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -244,11 +244,6 @@
CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
- /* e200 family */
- POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
- "PowerPC e200z5 core")
- POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
- "PowerPC e200z6 core")
/* e300 family */
POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
"PowerPC e300c1 core")
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 3aa3aefc136..c3284bcbd3f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1825,7 +1825,7 @@ static void init_excp_G2(CPUPPCState *env)
#endif
}
-static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
+static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask)
{
#if !defined(CONFIG_USER_ONLY)
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
@@ -2796,149 +2796,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_e200(CPUPPCState *env)
-{
- register_BookE_sprs(env, 0x000000070000FFFFULL);
-
- spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
- &spr_read_spefscr, &spr_write_spefscr,
- &spr_read_spefscr, &spr_write_spefscr,
- 0x00000000);
- /* Memory management */
- register_BookE206_sprs(env, 0x0000005D, NULL, 0);
- register_usprgh_sprs(env);
-
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
- &spr_read_generic, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000); /* TOFIX */
-
- init_tlbs_emb(env);
- init_excp_e200(env, 0xFFFF0000UL);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-}
-
-POWERPC_FAMILY(e200)(ObjectClass *oc, const void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e200 core";
- pcc->init_proc = init_proc_e200;
- pcc->check_pow = check_pow_hid0;
- pcc->check_attn = check_attn_none;
- /*
- * XXX: unimplemented instructions:
- * dcblc
- * dcbtlst
- * dcbtstls
- * icblc
- * icbtls
- * tlbivax
- * all SPE multiply-accumulate instructions
- */
- pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
- PPC_SPE | PPC_SPE_SINGLE |
- PPC_WRTEE | PPC_RFDI |
- PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVAX |
- PPC_BOOKE;
- pcc->msr_mask = (1ull << MSR_UCLE) |
- (1ull << MSR_SPE) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE206;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_860;
- pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
enum fsl_e500_version {
fsl_e500v1,
fsl_e500v2,
@@ -3173,7 +3030,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
}
#endif
- init_excp_e200(env, ivpr_mask);
+ init_excp_e500(env, ivpr_mask);
/* Allocate hardware IRQ controller */
ppce500_irq_init(env_archcpu(env));
}
--
2.51.0Hi Thomas,
I am seeing below CI failure with this patch:
In file included from ../target/ppc/cpu_init.c:46:
In function ‘register_BookE206_sprs’,
inlined from ‘init_proc_e500’ at ../target/ppc/cpu_init.c:2910:5:
../target/ppc/spr_common.h:57:5: error: array subscript 3 is outside
array bounds of ‘uint32_t[2]’ {aka ‘unsigned int[2]’}
[-Werror=array-bounds=]
57 | _spr_register(env, num, name,
\
|
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | USR_ARG(uea_read) USR_ARG(uea_write)
\
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
59 | SYS_ARG(oea_read) SYS_ARG(oea_write)
\
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60 | SYS_ARG(hea_read) SYS_ARG(hea_write)
\
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
61 | KVM_ARG(one_reg_id) initial_value)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../target/ppc/spr_common.h:66:5: note: in expansion of macro
‘spr_register_kvm_hv’
66 | spr_register_kvm_hv(env, num, name, uea_read, uea_write,
oea_read, \
| ^~~~~~~~~~~~~~~~~~~
../target/ppc/spr_common.h:77:5: note: in expansion of macro
‘spr_register_kvm’
77 | spr_register_kvm(env, num, name, uea_read, uea_write,
\
| ^~~~~~~~~~~~~~~~
../target/ppc/cpu_init.c:894:9: note: in expansion of macro ‘spr_register’
894 | spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
| ^~~~~~~~~~~~
../target/ppc/cpu_init.c: In function ‘init_proc_e500’:
../target/ppc/cpu_init.c:2809:14: note: at offset 12 into object
‘tlbncfg’ of size 8
2809 | uint32_t tlbncfg[2];
| ^~~~~~~
In function ‘register_BookE206_sprs’,
inlined from ‘init_proc_e500’ at ../target/ppc/cpu_init.c:2910:5:
../target/ppc/spr_common.h:57:5: error: array subscript 2 is outside
array bounds of ‘uint32_t[2]’ {aka ‘unsigned int[2]’}
[-Werror=array-bounds=]
57 | _spr_register(env, num, name,
\
|
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | USR_ARG(uea_read) USR_ARG(uea_write)
\
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
59 | SYS_ARG(oea_read) SYS_ARG(oea_write)
\
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60 | SYS_ARG(hea_read) SYS_ARG(hea_write)
\
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
61 | KVM_ARG(one_reg_id) initial_value)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../target/ppc/spr_common.h:66:5: note: in expansion of macro
‘spr_register_kvm_hv’
66 | spr_register_kvm_hv(env, num, name, uea_read, uea_write,
oea_read, \
| ^~~~~~~~~~~~~~~~~~~
../target/ppc/spr_common.h:77:5: note: in expansion of macro
‘spr_register_kvm’
77 | spr_register_kvm(env, num, name, uea_read, uea_write,
\
| ^~~~~~~~~~~~~~~~
../target/ppc/cpu_init.c:900:9: note: in expansion of macro ‘spr_register’
900 | spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
| ^~~~~~~~~~~~
../target/ppc/cpu_init.c: In function ‘init_proc_e500’:
../target/ppc/cpu_init.c:2809:14: note: at offset 8 into object
‘tlbncfg’ of size 8
2809 | uint32_t tlbncfg[2];
| ^~~~~~~
cc1: all warnings being treated as errors
[1374/1838] Compiling C object
libqemu-ppc-softmmu.a.p/target_ppc_gdbstub.c.o
[1375/1838] Compiling C object
libqemu-ppc-softmmu.a.p/target_ppc_cpu-models.c.o
ninja: build stopped: subcommand failed.
make: *** [Makefile:168: run-ninja] Error 1
Cleaning up project directory and file based variables
00:00
ERROR: Job failed: exit code 1
Kindly take a look.
regards,
Harsh
On 10/17/25 20:15, Thomas Huth wrote:
> From: Thomas Huth <thuth@redhat.com>
>
> There is currently no machine in QEMU (except the "none" machine)
> that can be run with one of the e200 ppc CPUs - all machines either
> complain about an invalid CPU type or crash QEMU immediatly.
>
> Looking at the history of this CPU type, it seems like it has never
> been used in QEMU and only implemented as a placeholder (see e.g. the
> comment about unimplemented instructions in the POWERPC_FAMILY(e200)
> section of cpu_init.c). Being completely unused and unusable since
> such a long time, let's just remove it now.
>
> Note: The init_excp_e200() is used by the e500 CPUs, too, so we
> rename this function to init_excp_e500() instead of removing it.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> target/ppc/cpu-models.h | 4 --
> target/ppc/cpu-models.c | 5 --
> target/ppc/cpu_init.c | 147 +---------------------------------------
> 3 files changed, 2 insertions(+), 154 deletions(-)
>
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> index c6cd27f390e..a439eb37ee4 100644
> --- a/target/ppc/cpu-models.h
> +++ b/target/ppc/cpu-models.h
> @@ -120,10 +120,6 @@ enum {
> #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
> #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
> #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
> - /* e200 family */
> - /* e200 cores */
> - CPU_POWERPC_e200z5 = 0x81000000,
> - CPU_POWERPC_e200z6 = 0x81120000,
> /* e300 family */
> /* e300 cores */
> CPU_POWERPC_e300c1 = 0x00830010,
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index 89ae763c7f6..26b6debcfc9 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -244,11 +244,6 @@
> CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
> POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
> CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
> - /* e200 family */
> - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
> - "PowerPC e200z5 core")
> - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
> - "PowerPC e200z6 core")
> /* e300 family */
> POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
> "PowerPC e300c1 core")
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 3aa3aefc136..c3284bcbd3f 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -1825,7 +1825,7 @@ static void init_excp_G2(CPUPPCState *env)
> #endif
> }
>
> -static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
> +static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
> @@ -2796,149 +2796,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data)
> POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
> }
>
> -static void init_proc_e200(CPUPPCState *env)
> -{
> - register_BookE_sprs(env, 0x000000070000FFFFULL);
> -
> - spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
> - &spr_read_spefscr, &spr_write_spefscr,
> - &spr_read_spefscr, &spr_write_spefscr,
> - 0x00000000);
> - /* Memory management */
> - register_BookE206_sprs(env, 0x0000005D, NULL, 0);
> - register_usprgh_sprs(env);
> -
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
> - &spr_read_generic, SPR_NOACCESS,
> - &spr_read_generic, SPR_NOACCESS,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_IAC3, "IAC3",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_IAC4, "IAC4",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_MMUCSR0, "MMUCSR0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000); /* TOFIX */
> -
> - init_tlbs_emb(env);
> - init_excp_e200(env, 0xFFFF0000UL);
> - env->dcache_line_size = 32;
> - env->icache_line_size = 32;
> - /* XXX: TODO: allocate internal IRQ controller */
> -}
> -
> -POWERPC_FAMILY(e200)(ObjectClass *oc, const void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "e200 core";
> - pcc->init_proc = init_proc_e200;
> - pcc->check_pow = check_pow_hid0;
> - pcc->check_attn = check_attn_none;
> - /*
> - * XXX: unimplemented instructions:
> - * dcblc
> - * dcbtlst
> - * dcbtstls
> - * icblc
> - * icbtls
> - * tlbivax
> - * all SPE multiply-accumulate instructions
> - */
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
> - PPC_SPE | PPC_SPE_SINGLE |
> - PPC_WRTEE | PPC_RFDI |
> - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
> - PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
> - PPC_MEM_TLBSYNC | PPC_TLBIVAX |
> - PPC_BOOKE;
> - pcc->msr_mask = (1ull << MSR_UCLE) |
> - (1ull << MSR_SPE) |
> - (1ull << MSR_POW) |
> - (1ull << MSR_CE) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_DWE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR);
> - pcc->mmu_model = POWERPC_MMU_BOOKE206;
> - pcc->excp_model = POWERPC_EXCP_BOOKE;
> - pcc->bus_model = PPC_FLAGS_INPUT_BookE;
> - pcc->bfd_mach = bfd_mach_ppc_860;
> - pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
> - POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
> - POWERPC_FLAG_BUS_CLK;
> -}
> -
> enum fsl_e500_version {
> fsl_e500v1,
> fsl_e500v2,
> @@ -3173,7 +3030,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
> }
> #endif
>
> - init_excp_e200(env, ivpr_mask);
> + init_excp_e500(env, ivpr_mask);
> /* Allocate hardware IRQ controller */
> ppce500_irq_init(env_archcpu(env));
> }
On 23/10/2025 12.07, Harsh Prateek Bora wrote:
> Hi Thomas,
> I am seeing below CI failure with this patch:
>
> In file included from ../target/ppc/cpu_init.c:46:
> In function ‘register_BookE206_sprs’,
> inlined from ‘init_proc_e500’ at ../target/ppc/cpu_init.c:2910:5:
> ../target/ppc/spr_common.h:57:5: error: array subscript 3 is outside array
> bounds of ‘uint32_t[2]’ {aka ‘unsigned int[2]’} [-Werror=array-bounds=]
> 57 | _spr_register(env, num, name, \
> |
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 58 | USR_ARG(uea_read) USR_ARG(uea_write) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 59 | SYS_ARG(oea_read) SYS_ARG(oea_write) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 60 | SYS_ARG(hea_read) SYS_ARG(hea_write) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 61 | KVM_ARG(one_reg_id) initial_value)
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> ../target/ppc/spr_common.h:66:5: note: in expansion of macro
> ‘spr_register_kvm_hv’
> 66 | spr_register_kvm_hv(env, num, name, uea_read, uea_write,
> oea_read, \
> | ^~~~~~~~~~~~~~~~~~~
> ../target/ppc/spr_common.h:77:5: note: in expansion of macro ‘spr_register_kvm’
> 77 | spr_register_kvm(env, num, name, uea_read, uea_write,
> \
> | ^~~~~~~~~~~~~~~~
> ../target/ppc/cpu_init.c:894:9: note: in expansion of macro ‘spr_register’
> 894 | spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
> | ^~~~~~~~~~~~
> ../target/ppc/cpu_init.c: In function ‘init_proc_e500’:
> ../target/ppc/cpu_init.c:2809:14: note: at offset 12 into object ‘tlbncfg’
> of size 8
> 2809 | uint32_t tlbncfg[2];
> | ^~~~~~~
> In function ‘register_BookE206_sprs’,
> inlined from ‘init_proc_e500’ at ../target/ppc/cpu_init.c:2910:5:
> ../target/ppc/spr_common.h:57:5: error: array subscript 2 is outside array
> bounds of ‘uint32_t[2]’ {aka ‘unsigned int[2]’} [-Werror=array-bounds=]
> 57 | _spr_register(env, num, name, \
> |
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 58 | USR_ARG(uea_read) USR_ARG(uea_write) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 59 | SYS_ARG(oea_read) SYS_ARG(oea_write) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 60 | SYS_ARG(hea_read) SYS_ARG(hea_write) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 61 | KVM_ARG(one_reg_id) initial_value)
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> ../target/ppc/spr_common.h:66:5: note: in expansion of macro
> ‘spr_register_kvm_hv’
> 66 | spr_register_kvm_hv(env, num, name, uea_read, uea_write,
> oea_read, \
> | ^~~~~~~~~~~~~~~~~~~
> ../target/ppc/spr_common.h:77:5: note: in expansion of macro ‘spr_register_kvm’
> 77 | spr_register_kvm(env, num, name, uea_read, uea_write,
> \
> | ^~~~~~~~~~~~~~~~
> ../target/ppc/cpu_init.c:900:9: note: in expansion of macro ‘spr_register’
> 900 | spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
> | ^~~~~~~~~~~~
> ../target/ppc/cpu_init.c: In function ‘init_proc_e500’:
> ../target/ppc/cpu_init.c:2809:14: note: at offset 8 into object ‘tlbncfg’ of
> size 8
> 2809 | uint32_t tlbncfg[2];
> | ^~~~~~~
> cc1: all warnings being treated as errors
> [1374/1838] Compiling C object libqemu-ppc-softmmu.a.p/target_ppc_gdbstub.c.o
> [1375/1838] Compiling C object libqemu-ppc-softmmu.a.p/target_ppc_cpu-
> models.c.o
> ninja: build stopped: subcommand failed.
> make: *** [Makefile:168: run-ninja] Error 1
> Cleaning up project directory and file based variables
> 00:00
> ERROR: Job failed: exit code 1
>
> Kindly take a look.
Drat, I think I likely only tested it in a build folder where I had run
configure with --disable-werror earlier, that's why I didn't notice. Sorry
for that. I'll try to come up with a fix and send a v2 when it's ready.
Thomas
On 10/17/25 20:15, Thomas Huth wrote:
> From: Thomas Huth <thuth@redhat.com>
>
> There is currently no machine in QEMU (except the "none" machine)
> that can be run with one of the e200 ppc CPUs - all machines either
> complain about an invalid CPU type or crash QEMU immediatly.
>
> Looking at the history of this CPU type, it seems like it has never
> been used in QEMU and only implemented as a placeholder (see e.g. the
> comment about unimplemented instructions in the POWERPC_FAMILY(e200)
> section of cpu_init.c). Being completely unused and unusable since
> such a long time, let's just remove it now.
>
> Note: The init_excp_e200() is used by the e500 CPUs, too, so we
> rename this function to init_excp_e500() instead of removing it.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> target/ppc/cpu-models.h | 4 --
> target/ppc/cpu-models.c | 5 --
> target/ppc/cpu_init.c | 147 +---------------------------------------
> 3 files changed, 2 insertions(+), 154 deletions(-)
>
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> index c6cd27f390e..a439eb37ee4 100644
> --- a/target/ppc/cpu-models.h
> +++ b/target/ppc/cpu-models.h
> @@ -120,10 +120,6 @@ enum {
> #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
> #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
> #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
> - /* e200 family */
> - /* e200 cores */
> - CPU_POWERPC_e200z5 = 0x81000000,
> - CPU_POWERPC_e200z6 = 0x81120000,
> /* e300 family */
> /* e300 cores */
> CPU_POWERPC_e300c1 = 0x00830010,
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index 89ae763c7f6..26b6debcfc9 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -244,11 +244,6 @@
> CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
> POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
> CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
> - /* e200 family */
> - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
> - "PowerPC e200z5 core")
> - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
> - "PowerPC e200z6 core")
While I hope removal of e200 should be fine, I am thinking if we want to
deprecate it in this cycle and remove it in next ?
We did deprecate Power8E, Power8NVL recently for 10.2 though.
See commit:
commit 264a604e71636bd04bfbbe3cf887259f246dccb3
Author: Aditya Gupta <adityag@linux.ibm.com>
Date: Sat Jun 7 16:34:12 2025 +0530
target/ppc: Deprecate Power8E and Power8NVL
Otherwise, the patch looks fine to me.
regards,
Harsh
> /* e300 family */
> POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300,
> "PowerPC e300c1 core")
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 3aa3aefc136..c3284bcbd3f 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -1825,7 +1825,7 @@ static void init_excp_G2(CPUPPCState *env)
> #endif
> }
>
> -static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
> +static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
> @@ -2796,149 +2796,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data)
> POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
> }
>
> -static void init_proc_e200(CPUPPCState *env)
> -{
> - register_BookE_sprs(env, 0x000000070000FFFFULL);
> -
> - spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
> - &spr_read_spefscr, &spr_write_spefscr,
> - &spr_read_spefscr, &spr_write_spefscr,
> - 0x00000000);
> - /* Memory management */
> - register_BookE206_sprs(env, 0x0000005D, NULL, 0);
> - register_usprgh_sprs(env);
> -
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
> - &spr_read_generic, SPR_NOACCESS,
> - &spr_read_generic, SPR_NOACCESS,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_IAC3, "IAC3",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_BOOKE_IAC4, "IAC4",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -
> - spr_register(env, SPR_MMUCSR0, "MMUCSR0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000); /* TOFIX */
> -
> - init_tlbs_emb(env);
> - init_excp_e200(env, 0xFFFF0000UL);
> - env->dcache_line_size = 32;
> - env->icache_line_size = 32;
> - /* XXX: TODO: allocate internal IRQ controller */
> -}
> -
> -POWERPC_FAMILY(e200)(ObjectClass *oc, const void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "e200 core";
> - pcc->init_proc = init_proc_e200;
> - pcc->check_pow = check_pow_hid0;
> - pcc->check_attn = check_attn_none;
> - /*
> - * XXX: unimplemented instructions:
> - * dcblc
> - * dcbtlst
> - * dcbtstls
> - * icblc
> - * icbtls
> - * tlbivax
> - * all SPE multiply-accumulate instructions
> - */
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
> - PPC_SPE | PPC_SPE_SINGLE |
> - PPC_WRTEE | PPC_RFDI |
> - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
> - PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
> - PPC_MEM_TLBSYNC | PPC_TLBIVAX |
> - PPC_BOOKE;
> - pcc->msr_mask = (1ull << MSR_UCLE) |
> - (1ull << MSR_SPE) |
> - (1ull << MSR_POW) |
> - (1ull << MSR_CE) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_DWE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR);
> - pcc->mmu_model = POWERPC_MMU_BOOKE206;
> - pcc->excp_model = POWERPC_EXCP_BOOKE;
> - pcc->bus_model = PPC_FLAGS_INPUT_BookE;
> - pcc->bfd_mach = bfd_mach_ppc_860;
> - pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
> - POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
> - POWERPC_FLAG_BUS_CLK;
> -}
> -
> enum fsl_e500_version {
> fsl_e500v1,
> fsl_e500v2,
> @@ -3173,7 +3030,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
> }
> #endif
>
> - init_excp_e200(env, ivpr_mask);
> + init_excp_e500(env, ivpr_mask);
> /* Allocate hardware IRQ controller */
> ppce500_irq_init(env_archcpu(env));
> }
On 10/17/25 17:50, Harsh Prateek Bora wrote:
>
>
> On 10/17/25 20:15, Thomas Huth wrote:
>> From: Thomas Huth <thuth@redhat.com>
>>
>> There is currently no machine in QEMU (except the "none" machine)
>> that can be run with one of the e200 ppc CPUs - all machines either
>> complain about an invalid CPU type or crash QEMU immediatly.
>>
>> Looking at the history of this CPU type, it seems like it has never
>> been used in QEMU and only implemented as a placeholder (see e.g. the
>> comment about unimplemented instructions in the POWERPC_FAMILY(e200)
>> section of cpu_init.c). Being completely unused and unusable since
>> such a long time, let's just remove it now.
>>
>> Note: The init_excp_e200() is used by the e500 CPUs, too, so we
>> rename this function to init_excp_e500() instead of removing it.
>>
>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>> ---
>> target/ppc/cpu-models.h | 4 --
>> target/ppc/cpu-models.c | 5 --
>> target/ppc/cpu_init.c | 147 +---------------------------------------
>> 3 files changed, 2 insertions(+), 154 deletions(-)
>>
>> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
>> index c6cd27f390e..a439eb37ee4 100644
>> --- a/target/ppc/cpu-models.h
>> +++ b/target/ppc/cpu-models.h
>> @@ -120,10 +120,6 @@ enum {
>> #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
>> #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
>> #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
>> - /* e200 family */
>> - /* e200 cores */
>> - CPU_POWERPC_e200z5 = 0x81000000,
>> - CPU_POWERPC_e200z6 = 0x81120000,
>> /* e300 family */
>> /* e300 cores */
>> CPU_POWERPC_e300c1 = 0x00830010,
>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
>> index 89ae763c7f6..26b6debcfc9 100644
>> --- a/target/ppc/cpu-models.c
>> +++ b/target/ppc/cpu-models.c
>> @@ -244,11 +244,6 @@
>> CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
>> POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
>> CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
>> - /* e200 family */
>> - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
>> - "PowerPC e200z5 core")
>> - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
>> - "PowerPC e200z6 core")
>
> While I hope removal of e200 should be fine, I am thinking if we want to
> deprecate it in this cycle and remove it in next ?
Since it was never usable (I don't remember of any tests for these
CPUs), I agree with Thomas to bypass the deprecation process.
Thanks,
C.
On 10/18/25 11:31, Cédric Le Goater wrote:
> On 10/17/25 17:50, Harsh Prateek Bora wrote:
>>
>>
>> On 10/17/25 20:15, Thomas Huth wrote:
>>> From: Thomas Huth <thuth@redhat.com>
>>>
>>> There is currently no machine in QEMU (except the "none" machine)
>>> that can be run with one of the e200 ppc CPUs - all machines either
>>> complain about an invalid CPU type or crash QEMU immediatly.
>>>
>>> Looking at the history of this CPU type, it seems like it has never
>>> been used in QEMU and only implemented as a placeholder (see e.g. the
>>> comment about unimplemented instructions in the POWERPC_FAMILY(e200)
>>> section of cpu_init.c). Being completely unused and unusable since
>>> such a long time, let's just remove it now.
>>>
>>> Note: The init_excp_e200() is used by the e500 CPUs, too, so we
>>> rename this function to init_excp_e500() instead of removing it.
>>>
>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>> ---
>>> target/ppc/cpu-models.h | 4 --
>>> target/ppc/cpu-models.c | 5 --
>>> target/ppc/cpu_init.c | 147 +---------------------------------------
>>> 3 files changed, 2 insertions(+), 154 deletions(-)
>>>
>>> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
>>> index c6cd27f390e..a439eb37ee4 100644
>>> --- a/target/ppc/cpu-models.h
>>> +++ b/target/ppc/cpu-models.h
>>> @@ -120,10 +120,6 @@ enum {
>>> #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
>>> #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
>>> #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
>>> - /* e200 family */
>>> - /* e200 cores */
>>> - CPU_POWERPC_e200z5 = 0x81000000,
>>> - CPU_POWERPC_e200z6 = 0x81120000,
>>> /* e300 family */
>>> /* e300 cores */
>>> CPU_POWERPC_e300c1 = 0x00830010,
>>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
>>> index 89ae763c7f6..26b6debcfc9 100644
>>> --- a/target/ppc/cpu-models.c
>>> +++ b/target/ppc/cpu-models.c
>>> @@ -244,11 +244,6 @@
>>> CPU_POWERPC_MPC5200B_v20,
>>> POWERPC_SVR_5200B_v20, G2LE)
>>> POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
>>> CPU_POWERPC_MPC5200B_v21,
>>> POWERPC_SVR_5200B_v21, G2LE)
>>> - /* e200
>>> family */
>>> - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5,
>>> e200,
>>> - "PowerPC e200z5 core")
>>> - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6,
>>> e200,
>>> - "PowerPC e200z6 core")
>>
>> While I hope removal of e200 should be fine, I am thinking if we want to
>> deprecate it in this cycle and remove it in next ?
>
> Since it was never usable (I don't remember of any tests for these
> CPUs), I agree with Thomas to bypass the deprecation process.
>
Sure, reasonable.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>
>
> Thanks,
>
> C.
>
On 18/10/2025 08.07, Harsh Prateek Bora wrote:
>
>
> On 10/18/25 11:31, Cédric Le Goater wrote:
>> On 10/17/25 17:50, Harsh Prateek Bora wrote:
>>>
>>>
>>> On 10/17/25 20:15, Thomas Huth wrote:
>>>> From: Thomas Huth <thuth@redhat.com>
>>>>
>>>> There is currently no machine in QEMU (except the "none" machine)
>>>> that can be run with one of the e200 ppc CPUs - all machines either
>>>> complain about an invalid CPU type or crash QEMU immediatly.
>>>>
>>>> Looking at the history of this CPU type, it seems like it has never
>>>> been used in QEMU and only implemented as a placeholder (see e.g. the
>>>> comment about unimplemented instructions in the POWERPC_FAMILY(e200)
>>>> section of cpu_init.c). Being completely unused and unusable since
>>>> such a long time, let's just remove it now.
>>>>
>>>> Note: The init_excp_e200() is used by the e500 CPUs, too, so we
>>>> rename this function to init_excp_e500() instead of removing it.
>>>>
>>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>>> ---
>>>> target/ppc/cpu-models.h | 4 --
>>>> target/ppc/cpu-models.c | 5 --
>>>> target/ppc/cpu_init.c | 147 +---------------------------------------
>>>> 3 files changed, 2 insertions(+), 154 deletions(-)
>>>>
>>>> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
>>>> index c6cd27f390e..a439eb37ee4 100644
>>>> --- a/target/ppc/cpu-models.h
>>>> +++ b/target/ppc/cpu-models.h
>>>> @@ -120,10 +120,6 @@ enum {
>>>> #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
>>>> #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
>>>> #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
>>>> - /* e200 family */
>>>> - /* e200 cores */
>>>> - CPU_POWERPC_e200z5 = 0x81000000,
>>>> - CPU_POWERPC_e200z6 = 0x81120000,
>>>> /* e300 family */
>>>> /* e300 cores */
>>>> CPU_POWERPC_e300c1 = 0x00830010,
>>>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
>>>> index 89ae763c7f6..26b6debcfc9 100644
>>>> --- a/target/ppc/cpu-models.c
>>>> +++ b/target/ppc/cpu-models.c
>>>> @@ -244,11 +244,6 @@
>>>> CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20,
>>>> G2LE)
>>>> POWERPC_DEF_SVR("mpc5200b_v21", "MPC5200B v2.1",
>>>> CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21,
>>>> G2LE)
>>>> - /* e200
>>>> family */
>>>> - POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200,
>>>> - "PowerPC e200z5 core")
>>>> - POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200,
>>>> - "PowerPC e200z6 core")
>>>
>>> While I hope removal of e200 should be fine, I am thinking if we want to
>>> deprecate it in this cycle and remove it in next ?
>>
>> Since it was never usable (I don't remember of any tests for these
>> CPUs), I agree with Thomas to bypass the deprecation process.
Yes, that's what I was thinking, too: If nobody could have ever used it,
there's no point in marking it as deprecated first.
> Sure, reasonable.
>
> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Thanks!
Thomas
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