This patchseries adds SME2 support to the gdbstub. This is
fairly straightforward as the only thing we need to do is
expose the new ZT0 register in the XML in the way that gdb
documents that we should.

Patch 2 is a simple "check reads and writes" test case along
the lines of our existing SME tests. I don't think there are
any specific gdb version requirements here because the XML
should be enough for gdb to know it's a 64 byte vector.
(I also did a little manual testing with a program that
reads and writes the ZT0 value in guest code to confirm that
gdb interactions do the right thing.)

thanks
-- PMM

Peter Maydell (2):
  target/arm: Implement SME2 support in gdbstub
  tests/tcg/aarch64: Add test case for SME2 gdbstub registers

 target/arm/cpu.h                       |  1 +
 target/arm/internals.h                 |  3 +
 target/arm/gdbstub.c                   |  7 +++
 target/arm/gdbstub64.c                 | 76 ++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target      |  9 ++-
 tests/tcg/aarch64/gdbstub/test-sme2.py | 41 ++++++++++++++
 6 files changed, 136 insertions(+), 1 deletion(-)
 create mode 100644 tests/tcg/aarch64/gdbstub/test-sme2.py

-- 
2.43.0

On 10/16/25 05:21, Peter Maydell wrote:
> This patchseries adds SME2 support to the gdbstub. This is
> fairly straightforward as the only thing we need to do is
> expose the new ZT0 register in the XML in the way that gdb
> documents that we should.

We're also missing TPIDR2.

According to gdb/features/aarch64-tls.c, "org.gnu.gdb.aarch64.tls" should contain 2 
registers, tpidr and tpidr2.  Apparently the second is optional, and we should have been 
providing the "tls" with just tpidr all along.


r~