The following changes since commit 8109ebdb95c45d9062c7e6e7beae0ee571fca4f8:

  Merge tag 'pull-loongarch-20251015' of https://github.com/bibo-mao/qemu into staging (2025-10-15 14:49:51 -0700)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/single-binary-20251016

for you to fetch changes up to 3b283e98d7f3b1cec795bfac0213265e41fbecfe:

  mailmap: Unify Clément Mathieu--Drif emails (2025-10-16 14:08:44 +0200)

----------------------------------------------------------------
Various patches related to single binary work:

- Remove some VMSTATE_UINTTL() uses
- Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
- Expand TCGv to TCGv_i32 for 32-bit targets
- Remove some unnecessary checks on TARGET_LONG_BITS
- Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
- Expand MO_TE to either MO_BE or MO_LE

Also:

- Fix HPPA FMPYADD opcode
- Unify Clément Mathieu--Drif email addresses
----------------------------------------------------------------

Anton Johansson (1):
  target/riscv: Use 32 bits for misa extensions

Gabriel Brookman (1):
  target/hppa: correct size bit parity for fmpyadd

Philippe Mathieu-Daudé (73):
  accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
  target/alpha: Access CPUState::cpu_index via helper
  target/alpha: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64()
  target/hppa: Use hwaddr type for HPPATLBEntry::pa
  target/hppa: Have hppa_form_gva*() return vaddr type
  target/hppa: Explode MO_TExx -> MO_TE | MO_xx
  target/hppa: Conceal MO_TE within do_load()
  target/hppa: Conceal MO_TE within do_load_32/64()
  target/hppa: Conceal MO_TE within do_store()
  target/hppa: Conceal MO_TE within do_store_32/64()
  target/hppa: Introduce mo_endian() helper
  target/hppa: Replace MO_TE -> MO_BE
  target/loongarch: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64()
  target/loongarch: Remove target_ulong use in gen_goto_tb()
  target/loongarch: Remove target_ulong use in gdb_write_register
    handler
  target/loongarch: Do not use target_ulong type for LDDIR level
  target/m68k: Remove unused @cpu_exception_index TCGv
  target/m68k: Remove pointless @cpu_halted TCGv
  target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()
  target/microblaze: Remove target_ulong uses in
    get_phys_page_attrs_debug
  target/microblaze: Remove target_ulong use in gen_goto_tb()
  target/microblaze: Remove target_ulong use in helper_stackprot()
  target/microblaze: Have compute_ldst_addr_type[ab] return TCGv_i32
  target/microblaze: Have do_load/store() take a TCGv_i32 address
    argument
  target/microblaze: Convert CPUMBState::res_addr field to uint32_t type
  target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32()
  target/openrisc: Do not use target_ulong for @mr in MTSPR helper
  target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers
  target/openrisc: Remove target_ulong use in raise_mmu_exception()
  target/openrisc: Use vaddr type for $pc jumps
  target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code
  target/openrisc: Explode MO_TExx -> MO_TE | MO_xx
  target/openrisc: Conceal MO_TE within do_load()
  target/openrisc: Conceal MO_TE within do_store()
  target/openrisc: Introduce mo_endian() helper
  target/openrisc: Replace MO_TE -> MO_BE
  target/openrisc: Inline tcg_gen_trunc_i64_tl()
  target/openrisc: Replace target_ulong -> uint32_t
  target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check
  target/rx: Replace target_ulong -> vaddr for translator API uses
  target/rx: Use MemOp type in gen_ld[u]() and gen_st()
  target/rx: Propagate DisasContext to generated helpers
  target/rx: Propagate DisasContext to push() / pop()
  target/rx: Propagate DisasContext to gen_ld[u]() and gen_st()
  target/rx: Factor mo_endian() helper out
  target/rx: Replace MO_TE -> MO_LE
  target/rx: Expand TCG register definitions for 32-bit target
  target/rx: Un-inline various helpers
  target/s390x: Replace HOST_BIG_ENDIAN #ifdef with if() check
  target/sh4: Convert CPUSH4State::sr register to uint32_t type
  target/sh4: Remove target_ulong use in cpu_sh4_is_cached()
  target/sh4: Use hwaddr type for hardware addresses
  target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug
  target/sh4: Use vaddr type for TLB virtual addresses
  target/sh4: Remove target_ulong use in gen_goto_tb()
  target/sparc: Reduce inclusions of 'exec/cpu-common.h'
  target/tricore: Remove target_ulong use in gen_goto_tb()
  target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
  target/tricore: Remove target_ulong use in translate_insn() handler
  target/tricore: Remove target_ulong use in gen_addi_d()
  target/tricore: Remove unnecessary cast to target_ulong
  target/tricore: Replace target_ulong -> uint32_t in op_helper.c
  target/tricore: Declare registers as TCGv_i32
  target/tricore: Inline tcg_gen_ld32u_tl()
  target/tricore: Expand TCG helpers for 32-bit target
  target/tricore: Pass DisasContext as first argument
  target/tricore: Un-inline various helpers
  target/tricore: Expand TCGv type for 32-bit target
  target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls
  target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn()
  target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state()
  linux-user/microblaze: Fix little-endianness binary
  mailmap: Unify Clément Mathieu--Drif emails

 target/alpha/helper.h                         |    1 +
 target/hppa/cpu.h                             |   10 +-
 target/loongarch/cpu-mmu.h                    |    2 +-
 target/loongarch/tcg/helper.h                 |    2 +-
 target/microblaze/cpu.h                       |    2 +-
 target/microblaze/helper.h                    |    2 +-
 target/microblaze/mmu.h                       |    2 +-
 target/openrisc/cpu.h                         |   31 +-
 target/openrisc/helper.h                      |    8 +-
 target/riscv/cpu.h                            |    4 +-
 target/sh4/cpu.h                              |    6 +-
 target/sparc/cpu.h                            |    1 -
 target/hppa/insns.decode                      |    8 +-
 linux-user/microblaze/elfload.c               |    3 +-
 target/alpha/machine.c                        |   34 +-
 target/alpha/sys_helper.c                     |    5 +
 target/alpha/translate.c                      |   11 +-
 target/arm/tcg/translate-a64.c                |    8 +-
 target/arm/tcg/translate.c                    |    8 +-
 target/avr/translate.c                        |    7 +-
 target/hexagon/translate.c                    |    8 +-
 target/hppa/helper.c                          |    4 +-
 target/hppa/mem_helper.c                      |    2 +-
 target/hppa/translate.c                       |   24 +-
 target/loongarch/cpu_helper.c                 |    2 +-
 target/loongarch/gdbstub.c                    |    2 +-
 target/loongarch/machine.c                    |    4 +-
 target/loongarch/tcg/tlb_helper.c             |    4 +-
 target/loongarch/tcg/translate.c              |    6 +-
 target/m68k/translate.c                       |   17 +-
 target/microblaze/helper.c                    |    3 +-
 target/microblaze/machine.c                   |    6 +-
 target/microblaze/mmu.c                       |    4 +-
 target/microblaze/op_helper.c                 |    4 +-
 target/microblaze/translate.c                 |   83 +-
 target/mips/tcg/translate.c                   |    7 +-
 target/openrisc/fpu_helper.c                  |    8 +-
 target/openrisc/machine.c                     |   20 +-
 target/openrisc/mmu.c                         |    7 +-
 target/openrisc/sys_helper.c                  |    7 +-
 target/openrisc/translate.c                   |  463 +-
 target/ppc/translate.c                        |    7 +-
 target/riscv/translate.c                      |    9 +-
 target/riscv/vector_helper.c                  |   32 +-
 target/rx/translate.c                         |  462 +-
 target/s390x/tcg/translate.c                  |    6 +-
 target/sh4/helper.c                           |   34 +-
 target/sh4/translate.c                        |   10 +-
 target/sparc/helper.c                         |    1 +
 target/sparc/int64_helper.c                   |    1 +
 target/sparc/translate.c                      |    6 +-
 target/tricore/cpu.c                          |    2 +-
 target/tricore/helper.c                       |    4 +-
 target/tricore/op_helper.c                    |  219 +-
 target/tricore/translate.c                    | 3978 +++++++++--------
 target/xtensa/cpu.c                           |    6 +-
 target/xtensa/translate.c                     |    2 +-
 target/xtensa/xtensa-semi.c                   |   11 +-
 .../tcg/insn_trans/trans_privileged.c.inc     |    2 +-
 target/riscv/insn_trans/trans_rvv.c.inc       |   16 +-
 target/s390x/tcg/translate_vx.c.inc           |    6 +-
 .mailmap                                      |    1 +
 target/hppa/trace-events                      |    6 +-
 63 files changed, 2848 insertions(+), 2813 deletions(-)

-- 
2.51.0