在 2025/10/16 上午9:50, Bibo Mao 写道:
> Hardware page table walk (PTW for short) is one feature supported in
> Loongson 3C6000 system. With hardware PTW supported, if there is an TLB
> miss, hardware will take PTW and fill it in TLB if matched, report TLB
> exception if not matched.
>
> With hardware PTW supported, bit Present and Write in pte entry is HW bit.
> Bit Present means that the page is valid, and bit Write means that the
> page is writable. At the same time HW will set bit Valid with read access,
> bit Dirty will be set with write access.
> ---
> v4 ... v5:
> 1. Add common API update_tlb_index() in new patch 11, it is to partly
> flush QEMU TLB when update LoongArch odd/even TLB entry. And it can
> be used by both SW/HW PTW hardware.
> 2. Record TLB index if found and update TLB from this index during PTW.
>
> v3 ... v4:
> 1. Rebase the patch on the latest version.
> 2. Set PTW feature disabled on LA464 CPU by default, ON_OFF_AUTO_AUTO
> on max CPU type.
> 3. Add field tlb_index and mmu_index when searching TLB table in new
> patch 10
>
> v2 ... v3:
> 1. Reserve high 48-63 bit PTE attribute with huge page, which is
> discard and converted to physical address wrongly.
> 2. Reload PTE entry rather than restart hardware PTW if PTE entry is
> updated with other CPUs and qatomic_cmpxchg() fails.
> 3. Since Huge page bit is the same with Global bit, judge huge page from
> page table level rather than Huge page bit.
>
> v1 ... v2:
> 1. Add wrapper function loongarch_cmpxchg_phys(), and use
> qatomic_cmpxchg() API to update PTW access/dirty bit.
> 2. Add restart hardware PTW if qatomic_cmpxchg() fails
> 3. Rename loongarch_page_table_walker() with loongarch_ptw().
> 4. Add debug parameter in loongarch_ptw(), with debug mode it is to
> get physical address only. With normal mode, bit Valid and Dirty
> will be update.
> ---
> Bibo Mao (14):
> target/loongarch: Use auto method with PTW feature
> target/loongarch: Add CSR_PWCH write helper function
> target/loongarch: Add present and write bit with pte entry
> target/loongarch: Add function sptw_prepare_tlb before adding tlb
> entry
> target/loongarch: target/loongarch: Add common function
> get_tlb_random_index()
> target/loongarch: Add MMUContext parameter in fill_tlb_entry()
> target/loongarch: Add debug parameter with
> loongarch_page_table_walker()
> target/loongarch: Reserve higher 48 bit PTE attribute with huge page
> target/loongarch: Move last PTE lookup into page table walker loop
> target/loongarch: Add field tlb_index to record TLB search info
> target/loongarch: Add common interface update_tlb_index()
> target/loongarch: Add basic hardware PTW support
> target/loongarch: Update matched ptw bit A/D with PTW supported
> target/loongarch: Add bit A/D checking in TLB entry with PTW supported
>
> target/loongarch/cpu-csr.h | 4 +
> target/loongarch/cpu-mmu.h | 62 ++++++++
> target/loongarch/cpu.c | 25 +++
> target/loongarch/cpu.h | 2 +
> target/loongarch/cpu_helper.c | 146 ++++++++++++++---
> target/loongarch/tcg/csr_helper.c | 15 ++
> target/loongarch/tcg/helper.h | 1 +
> .../tcg/insn_trans/trans_privileged.c.inc | 1 +
> target/loongarch/tcg/tlb_helper.c | 148 ++++++++++++++----
> 9 files changed, 348 insertions(+), 56 deletions(-)
>
>
> base-commit: 8109ebdb95c45d9062c7e6e7beae0ee571fca4f8
For this series:
Reviewed-by: Song Gao <gaosong@loongson.cn>
Thanks.
Song Gao