As ssp holds a pointer, fix to 64 bits in size and make sure stores from
TCG use the correct size to avoid problems on big endian hosts.
Note, the cpu/ssp VMSTATE version is bumped, breaking migration from
older versions.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/riscv/cpu.h | 2 +-
target/riscv/machine.c | 6 +++---
target/riscv/insn_trans/trans_rvzicfiss.c.inc | 18 +++++++++++++-----
3 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d7a41e6db5..2a71393118 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -255,7 +255,7 @@ struct CPUArchState {
/* elp state for zicfilp extension */
bool elp;
/* shadow stack register for zicfiss extension */
- target_ulong ssp;
+ uint64_t ssp;
/* env place holder for extra word 2 during unwind */
target_ulong excp_uw2;
/* sw check code for sw check exception */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 1cf744c5f0..c55794c554 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -390,11 +390,11 @@ static bool ssp_needed(void *opaque)
static const VMStateDescription vmstate_ssp = {
.name = "cpu/ssp",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = ssp_needed,
.fields = (const VMStateField[]) {
- VMSTATE_UINTTL(env.ssp, RISCVCPU),
+ VMSTATE_UINT64(env.ssp, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/insn_trans/trans_rvzicfiss.c.inc
index f4a1c12ca0..fa1489037d 100644
--- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc
@@ -32,7 +32,9 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
TCGLabel *skip = gen_new_label();
uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;
TCGv data = tcg_temp_new();
- tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
+ TCGv_i64 wide_addr = tcg_temp_new_i64();
+ tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
+ tcg_gen_trunc_i64_tl(addr, wide_addr);
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
tcg_gen_qemu_ld_tl(data, addr, SS_MMU_INDEX(ctx),
mxl_memop(ctx) | MO_ALIGN);
@@ -45,7 +47,8 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
tcg_constant_i32(RISCV_EXCP_SW_CHECK));
gen_set_label(skip);
tcg_gen_addi_tl(addr, addr, tmp);
- tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
+ tcg_gen_ext_tl_i64(wide_addr, addr);
+ tcg_gen_st_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
return true;
}
@@ -59,12 +62,15 @@ static bool trans_sspush(DisasContext *ctx, arg_sspush *a)
TCGv addr = tcg_temp_new();
int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4;
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv_i64 wide_addr = tcg_temp_new_i64();
decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
- tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
+ tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
+ tcg_gen_trunc_i64_tl(addr, wide_addr);
tcg_gen_addi_tl(addr, addr, tmp);
tcg_gen_qemu_st_tl(data, addr, SS_MMU_INDEX(ctx),
mxl_memop(ctx) | MO_ALIGN);
- tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
+ tcg_gen_ext_tl_i64(wide_addr, addr);
+ tcg_gen_st_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
return true;
}
@@ -76,7 +82,9 @@ static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a)
}
TCGv dest = dest_gpr(ctx, a->rd);
- tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp));
+ TCGv_i64 wide_addr = tcg_temp_new_i64();
+ tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp));
+ tcg_gen_trunc_i64_tl(dest, wide_addr);
gen_set_gpr(ctx, a->rd, dest);
return true;
--
2.51.0