[v2] target/arm: Implement FEAT_SYSREG128

[PATCH v2 04/37] target/arm: Asserts for ARM_CP_128BIT in define_one_arm_cp_reg

Posted by Richard Henderson 1 month ago

128-bit registers are aarch64 only; disallow non-zero reset values.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8c0b8889db..3b06704963 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7805,6 +7805,22 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
     assert(r->state == ARM_CP_STATE_AA32 || !(r->type & ARM_CP_64BIT));
     /* AArch32 64-bit registers have only CRm and Opc1 fields. */
     assert(!(r->type & ARM_CP_64BIT) || !(r->opc2 || r->crn));
+    if (r->type & ARM_CP_128BIT) {
+        /*
+         * Only AArch64 regs are 128-bit.  There is usually an AArch32 64-bit
+         * register aliasing the low half, which must be defined separately due
+         * to encoding conflicts above.
+         */
+        assert(r->state == ARM_CP_STATE_AA64);
+        /*
+         * All 128-bit regs are UNKNOWN at reset, so there's no need
+         * for either resetvalue or resetfn.  For those EL2 registers
+         * that become CONST RES0 for EL3 with EL2 disabled, we allow
+         * ARM_CP_CONST, but only with value 0.
+         */
+        assert(r->resetvalue == 0);
+        assert(r->resetfn == NULL);
+    }
     /* op0 only exists in the AArch64 encodings */
     assert(r->state != ARM_CP_STATE_AA32 || r->opc0 == 0);
 
-- 
2.43.0

Re: [PATCH v2 04/37] target/arm: Asserts for ARM_CP_128BIT in define_one_arm_cp_reg

Posted by Peter Maydell 4 weeks ago

On Tue, 14 Oct 2025 at 21:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> 128-bit registers are aarch64 only; disallow non-zero reset values.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8c0b8889db..3b06704963 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -7805,6 +7805,22 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
>      assert(r->state == ARM_CP_STATE_AA32 || !(r->type & ARM_CP_64BIT));
>      /* AArch32 64-bit registers have only CRm and Opc1 fields. */
>      assert(!(r->type & ARM_CP_64BIT) || !(r->opc2 || r->crn));
> +    if (r->type & ARM_CP_128BIT) {
> +        /*
> +         * Only AArch64 regs are 128-bit.  There is usually an AArch32 64-bit
> +         * register aliasing the low half, which must be defined separately due
> +         * to encoding conflicts above.
> +         */
> +        assert(r->state == ARM_CP_STATE_AA64);
> +        /*
> +         * All 128-bit regs are UNKNOWN at reset, so there's no need
> +         * for either resetvalue or resetfn.  For those EL2 registers
> +         * that become CONST RES0 for EL3 with EL2 disabled, we allow
> +         * ARM_CP_CONST, but only with value 0.

We might mention that QEMU chooses to always zero the regs
at reset.

> +         */
> +        assert(r->resetvalue == 0);
> +        assert(r->resetfn == NULL);


I assume that not permitting a non-zero reset value is just
"we don't need this yet, so don't bother writing code for it" ?

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [PATCH v2 04/37] target/arm: Asserts for ARM_CP_128BIT in define_one_arm_cp_reg

Posted by Richard Henderson 4 weeks ago

On 10/17/25 05:59, Peter Maydell wrote:
>> +        assert(r->resetvalue == 0);
>> +        assert(r->resetfn == NULL);
> 
> 
> I assume that not permitting a non-zero reset value is just
> "we don't need this yet, so don't bother writing code for it" ?

Yes.

r~