Based-on: 20251014195017.421681-1-richard.henderson@linaro.org
("[PATCH v2 0/7] target/arm: Implement FEAT_AIE")

Changes for v2:
  - The VHE rewrite has been merged.
  - The ARMCPU data are two separate uint64_t not Int128.
  - The write128fn callback uses two separate uint64_t arguments.
  - The read128fn callback continues to return Int128.
  - Updated arm_gdb_get_sysreg for 128-bit registers.

The final patch may be used to test all of this, but is not intended
for merge.  All of this should enabled if and only if FEAT_D128.


r~


Richard Henderson (37):
  target/arm: Implement isar tests for FEAT_SYSREG128, FEAT_SYSINSTR128
  target/arm: Define CP_REG_SIZE_U128
  target/arm: Update ARMCPRegInfo for 128-bit sysregs
  target/arm: Asserts for ARM_CP_128BIT in define_one_arm_cp_reg
  target/arm: Split add_cpreg_to_hashtable_aa64
  target/arm: Add raw_read128, raw_write128
  target/arm: Add read_raw_cp_reg128, write_raw_cp_reg128
  target/arm: Use cpreg_field_type in arm_gen_one_feature_sysreg
  target/arm: Merge arm_gen_one_feature_sysreg into the single caller
  target/arm: Handle MO_128 in arm_gdb_get_sysreg
  target/arm: Handle ARM_CP_128BIT in cpu reset
  target/arm: Put 128-bit sysregs into a separate list
  target/arm/kvm: Assert no 128-bit sysregs in kvm_arm_init_cpreg_list
  target/arm/hvf: Assert no 128-bit sysregs in hvf_arch_init_vcpu
  migration: Add vmstate_info_int128
  target/arm: Migrate cpreg128 registers
  target/arm: Add syn_aa64_sysreg128trap
  target/arm: Introduce helper_{get,set}_cp_reg128
  target/arm: Implement MRRS, MSRR, SYSP
  target/arm: Consolidate definitions of PAR
  target/arm: Extend PAR_EL1 to 128-bit
  target/arm: Consolidate definitions of TTBR[01]
  target/arm: Split out flush_if_asid_change
  target/arm: Use flush_if_asid_change in vmsa_ttbr_write
  target/arm: Extend TTBR system registers to 128-bit
  target/arm: Implement TLBIP IPAS2E1, IPAS2LE1
  target/arm: Implement TLBIP IPAS2E1IS, IPAS2LE1IS
  target/arm: Implement TLBIP RVAE1, RVAAE1, RVALE1, RVAALE1
  target/arm: Implement TLBIP RIPAS1E1, RIPAS1LE1, RIPAS2E1IS,
    RIPAS2LE1IS
  target/arm: Implement TLBIP RVA{L}E2{IS,OS}
  target/arm: Implement TLBIP RVA{L}E3{IS,OS}
  target/arm: Implement TLBIP VA{L}E1{IS,OS}
  target/arm: Implement TLBIP VAE2, VALE2
  target/arm: Implement TLBIP VAE3, VALE3
  target/arm: Implement TLBIP VA{L}E2{IS,OS}
  target/arm: Implement TLBIP VA{L}E3{IS,OS}
  NOTFORMERGE: Enable FEAT_SYSREG128, FEAT_SYSINSTR128 for cpu max

 include/migration/vmstate.h    |   1 +
 target/arm/cpregs.h            |  31 ++
 target/arm/cpu-features.h      |  10 +
 target/arm/cpu.h               |  33 +-
 target/arm/internals.h         |   1 +
 target/arm/kvm-consts.h        |   2 +
 target/arm/syndrome.h          |  10 +
 target/arm/tcg/helper.h        |   2 +
 migration/vmstate-types.c      |  30 ++
 target/arm/cpu.c               |  20 +-
 target/arm/gdbstub.c           |  87 +++--
 target/arm/helper.c            | 663 ++++++++++++++++++++++++++-------
 target/arm/hvf/hvf.c           |   4 +
 target/arm/kvm.c               |   2 +
 target/arm/machine.c           |  50 +++
 target/arm/tcg/cpregs-at.c     |   4 +
 target/arm/tcg/cpu64.c         |   2 +
 target/arm/tcg/op_helper.c     |  29 ++
 target/arm/tcg/tlb-insns.c     | 494 ++++++++++++++++++------
 target/arm/tcg/translate-a64.c | 169 +++++++--
 target/arm/tcg/a64.decode      |  12 +-
 21 files changed, 1312 insertions(+), 344 deletions(-)

-- 
2.43.0