On Sat, Oct 11, 2025 at 1:53 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> All callers of gen_fload_idx() / gen_fstore_idx() set the MO_TE flag.
> Set it once in the callees.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_xthead.c.inc | 18 ++++++++++--------
> 1 file changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
> index 70c563664ab..859cbc26cb2 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -349,6 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
> TCGv_i64 rd = cpu_fpr[a->rd];
> TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
>
> + memop |= MO_TE;
> tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
> if ((memop & MO_SIZE) == MO_32) {
> gen_nanbox_s(rd, rd);
> @@ -369,6 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
> TCGv_i64 rd = cpu_fpr[a->rd];
> TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
>
> + memop |= MO_TE;
> tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
>
> return true;
> @@ -379,7 +381,7 @@ static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
> - return gen_fload_idx(ctx, a, MO_TE | MO_UQ, false);
> + return gen_fload_idx(ctx, a, MO_UQ, false);
> }
>
> static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
> @@ -387,7 +389,7 @@ static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVF);
> - return gen_fload_idx(ctx, a, MO_TE | MO_UL, false);
> + return gen_fload_idx(ctx, a, MO_UL, false);
> }
>
> static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
> @@ -395,7 +397,7 @@ static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
> - return gen_fload_idx(ctx, a, MO_TE | MO_UQ, true);
> + return gen_fload_idx(ctx, a, MO_UQ, true);
> }
>
> static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
> @@ -403,7 +405,7 @@ static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVF);
> - return gen_fload_idx(ctx, a, MO_TE | MO_UL, true);
> + return gen_fload_idx(ctx, a, MO_UL, true);
> }
>
> static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
> @@ -411,7 +413,7 @@ static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
> - return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, false);
> + return gen_fstore_idx(ctx, a, MO_UQ, false);
> }
>
> static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
> @@ -419,7 +421,7 @@ static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVF);
> - return gen_fstore_idx(ctx, a, MO_TE | MO_UL, false);
> + return gen_fstore_idx(ctx, a, MO_UL, false);
> }
>
> static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
> @@ -427,7 +429,7 @@ static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
> - return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, true);
> + return gen_fstore_idx(ctx, a, MO_UQ, true);
> }
>
> static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
> @@ -435,7 +437,7 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
> REQUIRE_XTHEADFMEMIDX(ctx);
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVF);
> - return gen_fstore_idx(ctx, a, MO_TE | MO_UL, true);
> + return gen_fstore_idx(ctx, a, MO_UL, true);
> }
>
> /* XTheadFmv */
> --
> 2.51.0
>
>