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  3. [PATCH 00/13] target/riscv: Centralize MO_TE uses in a pair of helpers
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[PATCH 04/13] target/riscv: Conceal MO_TE within gen_inc()

Philippe Mathieu-Daudé posted 13 patches 1 month ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Christoph Muellner <christoph.muellner@vrull.eu>
[PATCH 04/13] target/riscv: Conceal MO_TE within gen_inc()
Posted by Philippe Mathieu-Daudé 1 month ago 
All callers of gen_inc() set the MO_TE flag. Set it once in
the callee.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++----------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index 754cb80e221..7e69906e5bf 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -568,6 +568,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
     TCGv rd = dest_gpr(ctx, a->rd);
     TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
 
+    memop |= MO_TE;
     tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
     tcg_gen_addi_tl(rs1, rs1, imm);
     gen_set_gpr(ctx, a->rd, rd);
@@ -588,6 +589,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
     TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
     TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
 
+    memop |= MO_TE;
     tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     tcg_gen_addi_tl(rs1, rs1, imm);
     gen_set_gpr(ctx, a->rs1, rs1);
@@ -598,64 +600,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
     REQUIRE_64BIT(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_SQ, false);
+    return gen_load_inc(ctx, a, MO_SQ, false);
 }
 
 static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
     REQUIRE_64BIT(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_SQ, true);
+    return gen_load_inc(ctx, a, MO_SQ, true);
 }
 
 static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_SL, false);
+    return gen_load_inc(ctx, a, MO_SL, false);
 }
 
 static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_SL, true);
+    return gen_load_inc(ctx, a, MO_SL, true);
 }
 
 static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
     REQUIRE_64BIT(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_UL, false);
+    return gen_load_inc(ctx, a, MO_UL, false);
 }
 
 static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
     REQUIRE_64BIT(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_UL, true);
+    return gen_load_inc(ctx, a, MO_UL, true);
 }
 
 static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_SW, false);
+    return gen_load_inc(ctx, a, MO_SW, false);
 }
 
 static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_SW, true);
+    return gen_load_inc(ctx, a, MO_SW, true);
 }
 
 static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_UW, false);
+    return gen_load_inc(ctx, a, MO_UW, false);
 }
 
 static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_load_inc(ctx, a, MO_TE | MO_UW, true);
+    return gen_load_inc(ctx, a, MO_UW, true);
 }
 
 static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a)
@@ -686,38 +688,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
     REQUIRE_64BIT(ctx);
-    return gen_store_inc(ctx, a, MO_TE | MO_SQ, false);
+    return gen_store_inc(ctx, a, MO_SQ, false);
 }
 
 static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
     REQUIRE_64BIT(ctx);
-    return gen_store_inc(ctx, a, MO_TE | MO_SQ, true);
+    return gen_store_inc(ctx, a, MO_SQ, true);
 }
 
 static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_store_inc(ctx, a, MO_TE | MO_SL, false);
+    return gen_store_inc(ctx, a, MO_SL, false);
 }
 
 static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_store_inc(ctx, a, MO_TE | MO_SL, true);
+    return gen_store_inc(ctx, a, MO_SL, true);
 }
 
 static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_store_inc(ctx, a, MO_TE | MO_SW, false);
+    return gen_store_inc(ctx, a, MO_SW, false);
 }
 
 static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a)
 {
     REQUIRE_XTHEADMEMIDX(ctx);
-    return gen_store_inc(ctx, a, MO_TE | MO_SW, true);
+    return gen_store_inc(ctx, a, MO_SW, true);
 }
 
 static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a)
-- 
2.51.0
Re: [PATCH 04/13] target/riscv: Conceal MO_TE within gen_inc()
Posted by Alistair Francis 1 month ago 
On Sat, Oct 11, 2025 at 1:53 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> All callers of gen_inc() set the MO_TE flag. Set it once in
> the callee.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++----------
>  1 file changed, 18 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
> index 754cb80e221..7e69906e5bf 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -568,6 +568,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
>      TCGv rd = dest_gpr(ctx, a->rd);
>      TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
>
> +    memop |= MO_TE;
>      tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
>      tcg_gen_addi_tl(rs1, rs1, imm);
>      gen_set_gpr(ctx, a->rd, rd);
> @@ -588,6 +589,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
>      TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
>      TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
>
> +    memop |= MO_TE;
>      tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
>      tcg_gen_addi_tl(rs1, rs1, imm);
>      gen_set_gpr(ctx, a->rs1, rs1);
> @@ -598,64 +600,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
>      REQUIRE_64BIT(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_SQ, false);
> +    return gen_load_inc(ctx, a, MO_SQ, false);
>  }
>
>  static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
>      REQUIRE_64BIT(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_SQ, true);
> +    return gen_load_inc(ctx, a, MO_SQ, true);
>  }
>
>  static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_SL, false);
> +    return gen_load_inc(ctx, a, MO_SL, false);
>  }
>
>  static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_SL, true);
> +    return gen_load_inc(ctx, a, MO_SL, true);
>  }
>
>  static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
>      REQUIRE_64BIT(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_UL, false);
> +    return gen_load_inc(ctx, a, MO_UL, false);
>  }
>
>  static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
>      REQUIRE_64BIT(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_UL, true);
> +    return gen_load_inc(ctx, a, MO_UL, true);
>  }
>
>  static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_SW, false);
> +    return gen_load_inc(ctx, a, MO_SW, false);
>  }
>
>  static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_SW, true);
> +    return gen_load_inc(ctx, a, MO_SW, true);
>  }
>
>  static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_UW, false);
> +    return gen_load_inc(ctx, a, MO_UW, false);
>  }
>
>  static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_load_inc(ctx, a, MO_TE | MO_UW, true);
> +    return gen_load_inc(ctx, a, MO_UW, true);
>  }
>
>  static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a)
> @@ -686,38 +688,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
>      REQUIRE_64BIT(ctx);
> -    return gen_store_inc(ctx, a, MO_TE | MO_SQ, false);
> +    return gen_store_inc(ctx, a, MO_SQ, false);
>  }
>
>  static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
>      REQUIRE_64BIT(ctx);
> -    return gen_store_inc(ctx, a, MO_TE | MO_SQ, true);
> +    return gen_store_inc(ctx, a, MO_SQ, true);
>  }
>
>  static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_store_inc(ctx, a, MO_TE | MO_SL, false);
> +    return gen_store_inc(ctx, a, MO_SL, false);
>  }
>
>  static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_store_inc(ctx, a, MO_TE | MO_SL, true);
> +    return gen_store_inc(ctx, a, MO_SL, true);
>  }
>
>  static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_store_inc(ctx, a, MO_TE | MO_SW, false);
> +    return gen_store_inc(ctx, a, MO_SW, false);
>  }
>
>  static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a)
>  {
>      REQUIRE_XTHEADMEMIDX(ctx);
> -    return gen_store_inc(ctx, a, MO_TE | MO_SW, true);
> +    return gen_store_inc(ctx, a, MO_SW, true);
>  }
>
>  static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a)
> --
> 2.51.0
>
>
Re: [PATCH 04/13] target/riscv: Conceal MO_TE within gen_inc()
Posted by Richard Henderson 1 month ago 
On 10/10/25 08:50, Philippe Mathieu-Daudé wrote:
> All callers of gen_inc() set the MO_TE flag. Set it once in
> the callee.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++----------
>   1 file changed, 18 insertions(+), 16 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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