On Fri, Oct 10, 2025 at 11:52 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Replace compile-time #ifdef with a runtime check to ensure all code
> paths are built and tested. This reduces build-time configuration
> complexity and improves maintainability.
>
> No functional change intended.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 32 ++++++++++++-------------
> target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++-------
> 2 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 41ea2231067..2de3358ee86 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -235,26 +235,26 @@ vext_continuous_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host,
> void *vd, uint32_t evl, uint32_t reg_start, void *host,
> uint32_t esz, bool is_load)
> {
> -#if HOST_BIG_ENDIAN
> - for (; reg_start < evl; reg_start++, host += esz) {
> - ldst_host(vd, reg_start, host);
> - }
> -#else
> - if (esz == 1) {
> - uint32_t byte_offset = reg_start * esz;
> - uint32_t size = (evl - reg_start) * esz;
> -
> - if (is_load) {
> - memcpy(vd + byte_offset, host, size);
> - } else {
> - memcpy(host, vd + byte_offset, size);
> - }
> - } else {
> + if (HOST_BIG_ENDIAN) {
> for (; reg_start < evl; reg_start++, host += esz) {
> ldst_host(vd, reg_start, host);
> }
> + } else {
> + if (esz == 1) {
> + uint32_t byte_offset = reg_start * esz;
> + uint32_t size = (evl - reg_start) * esz;
> +
> + if (is_load) {
> + memcpy(vd + byte_offset, host, size);
> + } else {
> + memcpy(host, vd + byte_offset, size);
> + }
> + } else {
> + for (; reg_start < evl; reg_start++, host += esz) {
> + ldst_host(vd, reg_start, host);
> + }
> + }
> }
> -#endif
> }
>
> static void vext_set_tail_elems_1s(target_ulong vl, void *vd,
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index f4b5460340e..2a487179f63 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3351,19 +3351,19 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
> /* offset of the idx element with base register r */
> static uint32_t endian_ofs(DisasContext *s, int r, int idx)
> {
> -#if HOST_BIG_ENDIAN
> - return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
> -#else
> - return vreg_ofs(s, r) + (idx << s->sew);
> -#endif
> + if (HOST_BIG_ENDIAN) {
> + return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
> + } else {
> + return vreg_ofs(s, r) + (idx << s->sew);
> + }
> }
>
> /* adjust the index according to the endian */
> static void endian_adjust(TCGv_i32 ofs, int sew)
> {
> -#if HOST_BIG_ENDIAN
> - tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
> -#endif
> + if (HOST_BIG_ENDIAN) {
> + tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
> + }
> }
>
> /* Load idx >= VLMAX ? 0 : vreg[idx] */
> --
> 2.51.0
>
>