Add a new AspeedCoprocessor class that defines the foundational structure for
ASPEED coprocessor models. This class encapsulates a base DeviceState with
links to system memory, clock, and peripheral components such as SCU, SCUIO,
Timer Controller, and UARTs.
Introduce the corresponding implementation file
aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize()
method, property registration, and QOM type registration. The class is marked
as abstract and intended to serve as a common base for specific coprocessor
variants (e.g. SSP/TSP subsystems).
This establishes a reusable and extensible framework for modeling ASPEED
coprocessor devices.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 45 ++++++++++++++++++++++++++
hw/arm/aspeed_coprocessor_common.c | 49 +++++++++++++++++++++++++++++
hw/arm/meson.build | 3 +-
3 files changed, 96 insertions(+), 1 deletion(-)
create mode 100644 include/hw/arm/aspeed_coprocessor.h
create mode 100644 hw/arm/aspeed_coprocessor_common.c
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
new file mode 100644
index 0000000000..6938dfe24c
--- /dev/null
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -0,0 +1,45 @@
+/*
+ * ASPEED Coprocessor
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_COPROCESSOR_H
+#define ASPEED_COPROCESSOR_H
+
+#include "qom/object.h"
+#include "hw/arm/aspeed_soc.h"
+
+struct AspeedCoprocessorState {
+ DeviceState parent;
+
+ MemoryRegion *memory;
+ MemoryRegion sram;
+ Clock *sysclk;
+
+ AspeedSCUState scu;
+ AspeedSCUState scuio;
+ AspeedTimerCtrlState timerctrl;
+ SerialMM uart[ASPEED_UARTS_NUM];
+};
+
+#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
+OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
+ ASPEED_COPROCESSOR)
+
+struct AspeedCoprocessorClass {
+ DeviceClass parent_class;
+
+ /** valid_cpu_types: NULL terminated array of a single CPU type. */
+ const char * const *valid_cpu_types;
+ uint32_t silicon_rev;
+ const hwaddr *memmap;
+ const int *irqmap;
+ int uarts_base;
+ int uarts_num;
+ qemu_irq (*get_irq)(void *ctx, int dev);
+};
+
+#endif /* ASPEED_COPROCESSOR_H */
diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
new file mode 100644
index 0000000000..8a94b44f07
--- /dev/null
+++ b/hw/arm/aspeed_coprocessor_common.c
@@ -0,0 +1,49 @@
+/*
+ * ASPEED Coprocessor
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "system/memory.h"
+#include "hw/qdev-properties.h"
+#include "hw/arm/aspeed_coprocessor.h"
+
+static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
+{
+ AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
+
+ if (!s->memory) {
+ error_setg(errp, "'memory' link is not set");
+ return;
+ }
+}
+
+static const Property aspeed_coprocessor_properties[] = {
+ DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
+ TYPE_MEMORY_REGION, MemoryRegion *),
+};
+
+static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_coprocessor_realize;
+ device_class_set_props(dc, aspeed_coprocessor_properties);
+}
+
+static const TypeInfo aspeed_coprocessor_types[] = {
+ {
+ .name = TYPE_ASPEED_COPROCESSOR,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AspeedCoprocessorState),
+ .class_size = sizeof(AspeedCoprocessorClass),
+ .class_init = aspeed_coprocessor_class_init,
+ .abstract = true,
+ },
+};
+
+DEFINE_TYPES(aspeed_coprocessor_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index dc68391305..0b2c66e391 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
- 'aspeed_ast27x0-fc.c',))
+ 'aspeed_ast27x0-fc.c',
+ 'aspeed_coprocessor_common.c',))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
--
2.43.0Jamin,
On 10/8/25 05:21, Jamin Lin wrote:
> Add a new AspeedCoprocessor class that defines the foundational structure for
> ASPEED coprocessor models. This class encapsulates a base DeviceState with
> links to system memory, clock, and peripheral components such as SCU, SCUIO,
> Timer Controller, and UARTs.
>
> Introduce the corresponding implementation file
> aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize()
> method, property registration, and QOM type registration. The class is marked
> as abstract and intended to serve as a common base for specific coprocessor
> variants (e.g. SSP/TSP subsystems).
>
> This establishes a reusable and extensible framework for modeling ASPEED
> coprocessor devices.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/arm/aspeed_coprocessor.h | 45 ++++++++++++++++++++++++++
> hw/arm/aspeed_coprocessor_common.c | 49 +++++++++++++++++++++++++++++
> hw/arm/meson.build | 3 +-
> 3 files changed, 96 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/arm/aspeed_coprocessor.h
> create mode 100644 hw/arm/aspeed_coprocessor_common.c
>
> diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
> new file mode 100644
> index 0000000000..6938dfe24c
> --- /dev/null
> +++ b/include/hw/arm/aspeed_coprocessor.h
> @@ -0,0 +1,45 @@
> +/*
> + * ASPEED Coprocessor
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef ASPEED_COPROCESSOR_H
> +#define ASPEED_COPROCESSOR_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/aspeed_soc.h"
> +
> +struct AspeedCoprocessorState {
> + DeviceState parent;
> +
> + MemoryRegion *memory;
> + MemoryRegion sram;
> + Clock *sysclk;
> +
> + AspeedSCUState scu;
> + AspeedSCUState scuio;
> + AspeedTimerCtrlState timerctrl;
> + SerialMM uart[ASPEED_UARTS_NUM];
> +};
> +
> +#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
> +OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
> + ASPEED_COPROCESSOR)
> +
> +struct AspeedCoprocessorClass {
> + DeviceClass parent_class;
> +
> + /** valid_cpu_types: NULL terminated array of a single CPU type. */
> + const char * const *valid_cpu_types;
> + uint32_t silicon_rev;
> + const hwaddr *memmap;
> + const int *irqmap;
> + int uarts_base;
> + int uarts_num;
> + qemu_irq (*get_irq)(void *ctx, int dev);
> +};
> +
> +#endif /* ASPEED_COPROCESSOR_H */
> diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
> new file mode 100644
> index 0000000000..8a94b44f07
> --- /dev/null
> +++ b/hw/arm/aspeed_coprocessor_common.c
> @@ -0,0 +1,49 @@
> +/*
> + * ASPEED Coprocessor
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "system/memory.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/arm/aspeed_coprocessor.h"
> +
> +static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
> +
> + if (!s->memory) {
> + error_setg(errp, "'memory' link is not set");
> + return;
> + }
> +}
> +
> +static const Property aspeed_coprocessor_properties[] = {
> + DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
> + TYPE_MEMORY_REGION, MemoryRegion *),
> +};
> +
> +static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = aspeed_coprocessor_realize;
> + device_class_set_props(dc, aspeed_coprocessor_properties);
> +}
> +
> +static const TypeInfo aspeed_coprocessor_types[] = {
> + {
> + .name = TYPE_ASPEED_COPROCESSOR,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(AspeedCoprocessorState),
> + .class_size = sizeof(AspeedCoprocessorClass),
> + .class_init = aspeed_coprocessor_class_init,
> + .abstract = true,
> + },
> +};
> +
> +DEFINE_TYPES(aspeed_coprocessor_types)
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index dc68391305..0b2c66e391 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'fby35.c'))
> arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
> 'aspeed_ast27x0.c',
> - 'aspeed_ast27x0-fc.c',))
> + 'aspeed_ast27x0-fc.c',
> + 'aspeed_coprocessor_common.c',))
I don't think we need to keep the ending comma ','.
More important, this list lacks source files :
'aspeed_ast27x0-ssp.c',
'aspeed_ast27x0-tsp.c',
which are aarch64 specific and with the following changes of this
series, 'make check' fails with :
Type 'aspeed27x0ssp-soc' is missing its parent 'aspeed-coprocessor'
A preliminary fix is needed.
Please run 'make check' before sending.
Thanks,
C.
> arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
> arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
> arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
Hi Cédric
> AspeedCoprocessor class and base implementation
>
> Jamin,
>
> On 10/8/25 05:21, Jamin Lin wrote:
> > Add a new AspeedCoprocessor class that defines the foundational
> > structure for ASPEED coprocessor models. This class encapsulates a
> > base DeviceState with links to system memory, clock, and peripheral
> > components such as SCU, SCUIO, Timer Controller, and UARTs.
> >
> > Introduce the corresponding implementation file
> > aspeed_coprocessor_common.c, which provides the
> > aspeed_coprocessor_realize() method, property registration, and QOM
> > type registration. The class is marked as abstract and intended to
> > serve as a common base for specific coprocessor variants (e.g. SSP/TSP
> subsystems).
> >
> > This establishes a reusable and extensible framework for modeling
> > ASPEED coprocessor devices.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_coprocessor.h | 45
> ++++++++++++++++++++++++++
> > hw/arm/aspeed_coprocessor_common.c | 49
> +++++++++++++++++++++++++++++
> > hw/arm/meson.build | 3 +-
> > 3 files changed, 96 insertions(+), 1 deletion(-)
> > create mode 100644 include/hw/arm/aspeed_coprocessor.h
> > create mode 100644 hw/arm/aspeed_coprocessor_common.c
> >
> > diff --git a/include/hw/arm/aspeed_coprocessor.h
> > b/include/hw/arm/aspeed_coprocessor.h
> > new file mode 100644
> > index 0000000000..6938dfe24c
> > --- /dev/null
> > +++ b/include/hw/arm/aspeed_coprocessor.h
> > @@ -0,0 +1,45 @@
> > +/*
> > + * ASPEED Coprocessor
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later */
> > +
> > +#ifndef ASPEED_COPROCESSOR_H
> > +#define ASPEED_COPROCESSOR_H
> > +
> > +#include "qom/object.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +
> > +struct AspeedCoprocessorState {
> > + DeviceState parent;
> > +
> > + MemoryRegion *memory;
> > + MemoryRegion sram;
> > + Clock *sysclk;
> > +
> > + AspeedSCUState scu;
> > + AspeedSCUState scuio;
> > + AspeedTimerCtrlState timerctrl;
> > + SerialMM uart[ASPEED_UARTS_NUM];
> > +};
> > +
> > +#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
> > +OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
> > + ASPEED_COPROCESSOR)
> > +
> > +struct AspeedCoprocessorClass {
> > + DeviceClass parent_class;
> > +
> > + /** valid_cpu_types: NULL terminated array of a single CPU type. */
> > + const char * const *valid_cpu_types;
> > + uint32_t silicon_rev;
> > + const hwaddr *memmap;
> > + const int *irqmap;
> > + int uarts_base;
> > + int uarts_num;
> > + qemu_irq (*get_irq)(void *ctx, int dev); };
> > +
> > +#endif /* ASPEED_COPROCESSOR_H */
> > diff --git a/hw/arm/aspeed_coprocessor_common.c
> > b/hw/arm/aspeed_coprocessor_common.c
> > new file mode 100644
> > index 0000000000..8a94b44f07
> > --- /dev/null
> > +++ b/hw/arm/aspeed_coprocessor_common.c
> > @@ -0,0 +1,49 @@
> > +/*
> > + * ASPEED Coprocessor
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "system/memory.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/arm/aspeed_coprocessor.h"
> > +
> > +static void aspeed_coprocessor_realize(DeviceState *dev, Error
> > +**errp) {
> > + AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
> > +
> > + if (!s->memory) {
> > + error_setg(errp, "'memory' link is not set");
> > + return;
> > + }
> > +}
> > +
> > +static const Property aspeed_coprocessor_properties[] = {
> > + DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
> > + TYPE_MEMORY_REGION, MemoryRegion *), };
> > +
> > +static void aspeed_coprocessor_class_init(ObjectClass *oc, const void
> > +*data) {
> > + DeviceClass *dc = DEVICE_CLASS(oc);
> > +
> > + dc->realize = aspeed_coprocessor_realize;
> > + device_class_set_props(dc, aspeed_coprocessor_properties); }
> > +
> > +static const TypeInfo aspeed_coprocessor_types[] = {
> > + {
> > + .name = TYPE_ASPEED_COPROCESSOR,
> > + .parent = TYPE_DEVICE,
> > + .instance_size = sizeof(AspeedCoprocessorState),
> > + .class_size = sizeof(AspeedCoprocessorClass),
> > + .class_init = aspeed_coprocessor_class_init,
> > + .abstract = true,
> > + },
> > +};
> > +
> > +DEFINE_TYPES(aspeed_coprocessor_types)
> > diff --git a/hw/arm/meson.build b/hw/arm/meson.build index
> > dc68391305..0b2c66e391 100644
> > --- a/hw/arm/meson.build
> > +++ b/hw/arm/meson.build
> > @@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true:
> files(
> > 'fby35.c'))
> > arm_common_ss.add(when: ['CONFIG_ASPEED_SOC',
> 'TARGET_AARCH64'], if_true: files(
> > 'aspeed_ast27x0.c',
> > - 'aspeed_ast27x0-fc.c',))
> > + 'aspeed_ast27x0-fc.c',
> > + 'aspeed_coprocessor_common.c',))
>
> I don't think we need to keep the ending comma ','.
>
>
> More important, this list lacks source files :
>
> 'aspeed_ast27x0-ssp.c',
> 'aspeed_ast27x0-tsp.c',
>
> which are aarch64 specific and with the following changes of this series, 'make
> check' fails with :
>
> Type 'aspeed27x0ssp-soc' is missing its parent 'aspeed-coprocessor'
>
> A preliminary fix is needed.
>
> Please run 'make check' before sending.
>
Thanks for reporting this issue.
I’ll run the tests and resend v2.
Jamin
> Thanks,
>
> C.
>
>
>
>
> > arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
> > arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
> > arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
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