Hi; here's the target-arm queue. This is a little bigger than
I prefer, but the bulk of it is Luc's versal2 series.
thanks
-- PMM
The following changes since commit eb7abb4a719f93ddd56571bf91681044b4159399:
hw/intc/loongarch_dintc: Set class_size for LoongArchDINTCClass (2025-10-06 13:54:50 -0700)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20251007
for you to fetch changes up to 932cac41ca633f24f192a69770bf91b55c4d27bb:
target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme (2025-10-07 11:26:10 +0100)
----------------------------------------------------------------
target-arm queue:
* target/arm: Don't set HCR.RW for AArch32 only CPUs
* new board model: amd-versal2-virt
* xlnx-zynqmp: model the GIC for the Cortex-R5 RPU cluster
* hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header
* Emulate FEAT_RME_GPC2
----------------------------------------------------------------
Clément Chigot (2):
hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header
hw/arm/xlnx-zynqmp: introduce helper to compute RPU number
Francisco Iglesias (1):
hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property
Frederic Konrad (1):
hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5
Luc Michel (46):
hw/arm/xlnx-versal: split the xlnx-versal type
hw/arm/xlnx-versal: prepare for FDT creation
hw/arm/xlnx-versal: uart: refactor creation
hw/arm/xlnx-versal: canfd: refactor creation
hw/arm/xlnx-versal: sdhci: refactor creation
hw/arm/xlnx-versal: gem: refactor creation
hw/arm/xlnx-versal: adma: refactor creation
hw/arm/xlnx-versal: xram: refactor creation
hw/arm/xlnx-versal: usb: refactor creation
hw/arm/xlnx-versal: efuse: refactor creation
hw/arm/xlnx-versal: ospi: refactor creation
hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs
hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation
hw/arm/xlnx-versal: bbram: refactor creation
hw/arm/xlnx-versal: trng: refactor creation
hw/arm/xlnx-versal: rtc: refactor creation
hw/arm/xlnx-versal: cfu: refactor creation
hw/arm/xlnx-versal: crl: refactor creation
hw/arm/xlnx-versal-virt: virtio: refactor creation
hw/arm/xlnx-versal: refactor CPU cluster creation
hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping
hw/arm/xlnx-versal: instantiate the GIC ITS in the APU
hw/arm/xlnx-versal: add support for multiple GICs
hw/arm/xlnx-versal: add support for GICv2
hw/arm/xlnx-versal: rpu: refactor creation
hw/arm/xlnx-versal: ocm: refactor creation
hw/arm/xlnx-versal: ddr: refactor creation
hw/arm/xlnx-versal: add the versal_get_num_cpu accessor
hw/misc/xlnx-versal-crl: remove unnecessary include directives
hw/misc/xlnx-versal-crl: split into base/concrete classes
hw/misc/xlnx-versal-crl: refactor device reset logic
hw/arm/xlnx-versal: reconnect the CRL to the other devices
hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices
hw/arm/xlnx-versal: tidy up
hw/misc/xlnx-versal-crl: add the versal2 version
hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap
hw/arm/xlnx-versal: add the target field in IRQ descriptor
target/arm/tcg/cpu64: add the cortex-a78ae CPU
hw/arm/xlnx-versal: add versal2 SoC
hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt
hw/arm/xlnx-versal-virt: split into base/concrete classes
hw/arm/xlnx-versal-virt: tidy up
docs/system/arm/xlnx-versal-virt: update supported devices
docs/system/arm/xlnx-versal-virt: add a note about dumpdtb
hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine
tests/functional/test_aarch64_xlnx_versal: test the versal2 machine
Peter Maydell (1):
target/arm: Don't set HCR.RW for AArch32 only CPUs
Philippe Mathieu-Daudé (1):
hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header
Richard Henderson (10):
target/arm: Add isar feature test for FEAT_RME_GPC2
target/arm: Add GPCCR fields from ARM revision L.b
target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write
target/arm: Add cur_space to S1Translate
target/arm: GPT_Secure is reserved without FEAT_SEL2
target/arm: Implement GPT_NonSecureOnly
target/arm: Implement SPAD, NSPAD, RLPAD
target/arm: Fix GPT fault type for address outside PPS
target/arm: Implement APPSAA
target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme
MAINTAINERS | 1 -
docs/system/arm/emulation.rst | 1 +
docs/system/arm/xlnx-versal-virt.rst | 80 +-
include/hw/arm/sharpsl.h | 17 -
include/hw/arm/xlnx-versal-version.h | 16 +
include/hw/arm/xlnx-versal.h | 342 +---
include/hw/arm/xlnx-zynqmp.h | 5 +
include/hw/intc/arm_gicv3_common.h | 1 +
include/hw/misc/xlnx-versal-crl.h | 366 +++-
target/arm/cpu-features.h | 5 +
target/arm/cpu.h | 6 +
hw/arm/xlnx-versal-virt.c | 741 ++------
hw/arm/xlnx-versal.c | 2546 +++++++++++++++++++-------
hw/arm/xlnx-zynqmp.c | 103 +-
hw/gpio/zaurus.c | 42 -
hw/intc/arm_gicv3_common.c | 3 +-
hw/intc/arm_gicv3_cpuif.c | 2 +-
hw/intc/arm_gicv3_kvm.c | 6 +
hw/misc/xlnx-versal-crl.c | 614 ++++++-
target/arm/helper.c | 8 +-
target/arm/ptw.c | 95 +-
target/arm/tcg/cpu64.c | 81 +-
tests/functional/aarch64/test_xlnx_versal.py | 12 +-
23 files changed, 3292 insertions(+), 1801 deletions(-)
delete mode 100644 include/hw/arm/sharpsl.h
create mode 100644 include/hw/arm/xlnx-versal-version.h