Add a new flag, ARM_CP_NV_NO_TRAP, to indicate that a CP register, even
though it has opc1 == 4 or 5, does not trap when nested virtualization
is enabled (FEAT_NV/FEAT_NV2).

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
---
 target/arm/cpregs.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 57fde5f57a..abee72c9bf 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -136,6 +136,7 @@ enum {
      * identically to the normal one, other than FGT trapping handling.)
      */
     ARM_CP_ADD_TLBI_NXS          = 1 << 21,
+    ARM_CP_NV_NO_TRAP            = 1 << 22,
 };
 
 /*
@@ -1158,10 +1159,14 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
      *
      * In particular, note that the released sysreg XML defines that
      * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV
-     * trapping rule, so we will need to add an ARM_CP_* flag to indicate
-     * "register does not trap on NV" to handle those if/when we implement
-     * FEAT_MEC.
+     * trapping rule, so a register flagged as ARM_CP_NV_NO_TRAP indicates
+     * the register does not trap on NV even if opc1 == 4 or 5.
      */
+
+    if (ri->type & ARM_CP_NV_NO_TRAP) {
+        return false;
+    }
+
     return ri->opc1 == 4 || ri->opc1 == 5;
 }
 
-- 
2.34.1

On Mon, 6 Oct 2025 at 01:10, Gustavo Romero <gustavo.romero@linaro.org> wrote:
>
> Add a new flag, ARM_CP_NV_NO_TRAP, to indicate that a CP register, even
> though it has opc1 == 4 or 5, does not trap when nested virtualization
> is enabled (FEAT_NV/FEAT_NV2).
>
> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
> ---
>  target/arm/cpregs.h | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
> index 57fde5f57a..abee72c9bf 100644
> --- a/target/arm/cpregs.h
> +++ b/target/arm/cpregs.h
> @@ -136,6 +136,7 @@ enum {
>       * identically to the normal one, other than FGT trapping handling.)
>       */
>      ARM_CP_ADD_TLBI_NXS          = 1 << 21,

We should have a comment here documenting the flag:

/*
 * Flag: even though this sysreg has opc1 == 4 or 5, it
 * should not trap to EL2 when HCR_EL2.NV is set.
 */

> +    ARM_CP_NV_NO_TRAP            = 1 << 22,
>  };
>
>  /*
> @@ -1158,10 +1159,14 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
>       *
>       * In particular, note that the released sysreg XML defines that
>       * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV
> -     * trapping rule, so we will need to add an ARM_CP_* flag to indicate
> -     * "register does not trap on NV" to handle those if/when we implement
> -     * FEAT_MEC.
> +     * trapping rule, so a register flagged as ARM_CP_NV_NO_TRAP indicates
> +     * the register does not trap on NV even if opc1 == 4 or 5.

FEAT_MEC is in the Arm ARM now, so we can drop the reference
to the sysreg XML while we're touching this comment:

    In particular, note that the FEAT_MEC sysregs and instructions
    are exceptions to this trapping rule, so they are marked as
    ARM_CP_NV_NO_TRAP to indicate that they should not be trapped
    to EL2.

>       */
> +
> +    if (ri->type & ARM_CP_NV_NO_TRAP) {
> +        return false;
> +    }
> +
>      return ri->opc1 == 4 || ri->opc1 == 5;
>  }

Code changes look good.

thanks
-- PMM