Fix Ethernet interface support for microchip-icicle-kit

[PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

Guenter Roeck posted 4 patches 1 month, 1 week ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251004200049.871646-1-linux@roeck-us.net

Maintainers: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>, Peter Maydell <peter.maydell@linaro.org>, Jason Wang <jasowang@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

hw/net/cadence_gem.c         | 31 ++++++++++++++++++++++++-------
hw/riscv/microchip_pfsoc.c   |  6 ++++++
include/hw/net/cadence_gem.h |  4 ++++
3 files changed, 34 insertions(+), 7 deletions(-)

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[PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

Posted by Guenter Roeck 1 month, 1 week ago

The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
The PHY on each may be connected to separate MDIO busses, or both may be
connected on the same MDIO bus using different PHY addresses. Add support
for it to the Cadence GEM emulation.

The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel. Add support for clearing the PCS disabled bit.

----------------------------------------------------------------
Guenter Roeck (4):
      hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
      hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
      hw/net/cadence_gem: Add pcs-enabled property
      microchip icicle: Enable PCS on Cadence Ethernet

 hw/net/cadence_gem.c         | 31 ++++++++++++++++++++++++-------
 hw/riscv/microchip_pfsoc.c   |  6 ++++++
 include/hw/net/cadence_gem.h |  4 ++++
 3 files changed, 34 insertions(+), 7 deletions(-)

Re: [PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

Posted by Alistair Francis 1 month ago

On Sun, Oct 5, 2025 at 6:02 AM Guenter Roeck <linux@roeck-us.net> wrote:
>
> The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
> The PHY on each may be connected to separate MDIO busses, or both may be
> connected on the same MDIO bus using different PHY addresses. Add support
> for it to the Cadence GEM emulation.
>
> The Linux kernel checks the PCS disabled bit in the R_DESCONF register
> to determine if SGMII is supported. If the bit is set, SGMII support is
> disabled. Since the Microchip Icicle devicetree file configures SGMII
> interface mode, enabling the Ethernet interfaces fails when booting
> the Linux kernel. Add support for clearing the PCS disabled bit.
>
> ----------------------------------------------------------------
> Guenter Roeck (4):
>       hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
>       hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
>       hw/net/cadence_gem: Add pcs-enabled property
>       microchip icicle: Enable PCS on Cadence Ethernet

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/net/cadence_gem.c         | 31 ++++++++++++++++++++++++-------
>  hw/riscv/microchip_pfsoc.c   |  6 ++++++
>  include/hw/net/cadence_gem.h |  4 ++++
>  3 files changed, 34 insertions(+), 7 deletions(-)
>

Re: [PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

Posted by Conor Dooley 1 month ago

On Wed, Oct 15, 2025 at 01:03:50PM +1000, Alistair Francis wrote:
> On Sun, Oct 5, 2025 at 6:02 AM Guenter Roeck <linux@roeck-us.net> wrote:
> >
> > The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
> > The PHY on each may be connected to separate MDIO busses, or both may be
> > connected on the same MDIO bus using different PHY addresses. Add support
> > for it to the Cadence GEM emulation.
> >
> > The Linux kernel checks the PCS disabled bit in the R_DESCONF register
> > to determine if SGMII is supported. If the bit is set, SGMII support is
> > disabled. Since the Microchip Icicle devicetree file configures SGMII
> > interface mode, enabling the Ethernet interfaces fails when booting
> > the Linux kernel. Add support for clearing the PCS disabled bit.
> >
> > ----------------------------------------------------------------
> > Guenter Roeck (4):
> >       hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
> >       hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
> >       hw/net/cadence_gem: Add pcs-enabled property
> >       microchip icicle: Enable PCS on Cadence Ethernet
> 
> Thanks!
> 
> Applied to riscv-to-apply.next

Didn't notice these in time, thanks for fixing this Guenter.