The following changes since commit 4975b64efb5aa4248cbc3760312bbe08d6e71638:

  Merge tag 'pull-loongarch-20250928' of https://github.com/bibo-mao/qemu into staging (2025-09-28 09:01:35 -0700)

are available in the Git repository at:

  https://github.com/legoater/qemu/ tags/pull-aspeed-20250929

for you to fetch changes up to 9ec30a07483640ecb8417fce3dfa9273f7a036c9:

  hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp (2025-09-29 18:00:20 +0200)

----------------------------------------------------------------
aspeed queue:

* Introduce a new ASPEED OTP memory device model integrated with the
  Secure Boot Controller. It includes a new block device backend
  ('drive' property), is enabled for AST2600 SoCs and AST1030 SoCs.
  Functional tests are included
* Changed "ast2700-evb" alias to point to the "ast2700a1-evb" machine
* Introduce support for Aspeed PCIe host controller, including models
  for the PCIe Root Complex, Root Port, and PHY. Enabled for the
  AST2600 and AST2700 SoCs, and functional tests are included
* Refactor Boot ROM support to improve code reuse across the different
  Aspeed machine. This is in preparation of vbootrom support in the
  ast2700fc machine
* Improved Error Handling in the AST27x0-fc machine init functions

----------------------------------------------------------------
Jamin Lin (20):
      hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb
      hw/pci/pci_ids: Add PCI vendor ID for ASPEED
      hw/pci-host/aspeed: Add AST2600 PCIe PHY model
      hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge
      hw/pci-host/aspeed: Add AST2600 PCIe Root Device support
      hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable
      hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
      hw/arm/aspeed: Wire up PCIe devices in SoC model
      hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)
      hw/pci-host/aspeed: Add AST2700 PCIe PHY
      hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks
      hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST2700
      hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700
      tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test
      hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC code
      hw/arm/aspeed: Move write_boot_rom to common SoC code
      hw/arm/aspeed: Move aspeed_install_boot_rom to common SoC code
      hw/arm/aspeed: Move aspeed_load_vbootrom to common SoC code
      hw/arm/aspeed_ast27x0-fc: Drop dead return checks
      hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp

Kane-Chen-AS (12):
      hw/nvram/aspeed_otp: Add ASPEED OTP memory device model
      hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
      hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
      hw/nvram/aspeed_otp: Add 'drive' property to support block backend
      hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
      hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
      hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
      hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers
      docs/system/arm/aspeed: Document OTP memory options
      tests/functional/arm: Add helper to generate OTP images
      tests/functional/arm: Add AST1030 boot test with generated OTP image
      tests/functional/arm: Add AST2600 boot test with generated OTP image

 docs/system/arm/aspeed.rst                      |   31 +
 include/hw/arm/aspeed_soc.h                     |   23 +
 include/hw/misc/aspeed_sbc.h                    |    6 +
 include/hw/nvram/aspeed_otp.h                   |   33 +
 include/hw/pci-host/aspeed_pcie.h               |  137 +++
 include/hw/pci/pci_ids.h                        |    2 +
 hw/arm/aspeed.c                                 |  107 +--
 hw/arm/aspeed_ast10x0.c                         |    2 +-
 hw/arm/aspeed_ast2600.c                         |   76 +-
 hw/arm/aspeed_ast27x0-fc.c                      |   77 +-
 hw/arm/aspeed_ast27x0.c                         |   74 ++
 hw/arm/aspeed_soc_common.c                      |   96 +++
 hw/misc/aspeed_sbc.c                            |  197 +++++
 hw/nvram/aspeed_otp.c                           |  190 +++++
 hw/pci-host/aspeed_pcie.c                       | 1015 +++++++++++++++++++++++
 hw/arm/Kconfig                                  |    3 +
 hw/misc/trace-events                            |    6 +
 hw/nvram/meson.build                            |    4 +
 hw/nvram/trace-events                           |    5 +
 hw/pci-host/Kconfig                             |    4 +
 hw/pci-host/meson.build                         |    1 +
 hw/pci-host/trace-events                        |   11 +
 tests/functional/aarch64/test_aspeed_ast2700.py |    4 +-
 tests/functional/arm/test_aspeed_ast1030.py     |   24 +-
 tests/functional/arm/test_aspeed_ast2600.py     |   36 +
 tests/functional/aspeed.py                      |    8 +
 26 files changed, 2019 insertions(+), 153 deletions(-)
 create mode 100644 include/hw/nvram/aspeed_otp.h
 create mode 100644 include/hw/pci-host/aspeed_pcie.h
 create mode 100644 hw/nvram/aspeed_otp.c
 create mode 100644 hw/pci-host/aspeed_pcie.c

On 9/29/25 09:51, Cédric Le Goater wrote:
> The following changes since commit 4975b64efb5aa4248cbc3760312bbe08d6e71638:
> 
>    Merge tag 'pull-loongarch-20250928' ofhttps://github.com/bibo-mao/qemu into staging (2025-09-28 09:01:35 -0700)
> 
> are available in the Git repository at:
> 
>    https://github.com/legoater/qemu/ tags/pull-aspeed-20250929
> 
> for you to fetch changes up to 9ec30a07483640ecb8417fce3dfa9273f7a036c9:
> 
>    hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp (2025-09-29 18:00:20 +0200)
> 
> ----------------------------------------------------------------
> aspeed queue:
> 
> * Introduce a new ASPEED OTP memory device model integrated with the
>    Secure Boot Controller. It includes a new block device backend
>    ('drive' property), is enabled for AST2600 SoCs and AST1030 SoCs.
>    Functional tests are included
> * Changed "ast2700-evb" alias to point to the "ast2700a1-evb" machine
> * Introduce support for Aspeed PCIe host controller, including models
>    for the PCIe Root Complex, Root Port, and PHY. Enabled for the
>    AST2600 and AST2700 SoCs, and functional tests are included
> * Refactor Boot ROM support to improve code reuse across the different
>    Aspeed machine. This is in preparation of vbootrom support in the
>    ast2700fc machine
> * Improved Error Handling in the AST27x0-fc machine init functions


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.

r~