[v2] hw/arm/smmuv3: Add initial support for Secure State

[PATCH v2 02/14] hw/arm/smmuv3: Correct SMMUEN field name in CR0

Posted by Tao Tang 2 days, 23 hours ago

The FIELD macro for the SMMU enable bit in the CR0 register was
incorrectly named SMMU_ENABLE.

The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and
newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN.

This change makes our implementation consistent with the manual.

Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
---
 hw/arm/smmuv3-internal.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 516f2ffa75..71a3c0c02c 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -116,7 +116,7 @@ REG32(IDR5,                0x14)
 REG32(IIDR,                0x18)
 REG32(AIDR,                0x1c)
 REG32(CR0,                 0x20)
-    FIELD(CR0, SMMU_ENABLE,   0, 1)
+    FIELD(CR0, SMMUEN,   0, 1)
     FIELD(CR0, EVENTQEN,      2, 1)
     FIELD(CR0, CMDQEN,        3, 1)
 
@@ -182,7 +182,7 @@ REG32(EVENTQ_IRQ_CFG2,     0xbc)
 
 static inline int smmu_enabled(SMMUv3State *s)
 {
-    return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
+    return FIELD_EX32(s->cr[0], CR0, SMMUEN);
 }
 
 /* Command Queue Entry */
-- 
2.34.1

Re: [PATCH v2 02/14] hw/arm/smmuv3: Correct SMMUEN field name in CR0

Posted by Eric Auger 2 days, 2 hours ago

Hi Tao,

On 9/25/25 6:26 PM, Tao Tang wrote:
> The FIELD macro for the SMMU enable bit in the CR0 register was
> incorrectly named SMMU_ENABLE.
>
> The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and
> newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN.
>
> This change makes our implementation consistent with the manual.
>
> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  hw/arm/smmuv3-internal.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
> index 516f2ffa75..71a3c0c02c 100644
> --- a/hw/arm/smmuv3-internal.h
> +++ b/hw/arm/smmuv3-internal.h
> @@ -116,7 +116,7 @@ REG32(IDR5,                0x14)
>  REG32(IIDR,                0x18)
>  REG32(AIDR,                0x1c)
>  REG32(CR0,                 0x20)
> -    FIELD(CR0, SMMU_ENABLE,   0, 1)
> +    FIELD(CR0, SMMUEN,   0, 1)
>      FIELD(CR0, EVENTQEN,      2, 1)
>      FIELD(CR0, CMDQEN,        3, 1)
>  
> @@ -182,7 +182,7 @@ REG32(EVENTQ_IRQ_CFG2,     0xbc)
>  
>  static inline int smmu_enabled(SMMUv3State *s)
>  {
> -    return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
> +    return FIELD_EX32(s->cr[0], CR0, SMMUEN);
>  }
>  
>  /* Command Queue Entry */