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[PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs

Coco Li posted 5 patches 4 months, 2 weeks ago
Maintainers: Tyrone Ting <kfting@nuvoton.com>, Hao Wu <wuhaotsh@google.com>, Peter Maydell <peter.maydell@linaro.org>, "Cédric Le Goater" <clg@kaod.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>, Markus Armbruster <armbru@redhat.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>
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[PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs
Posted by Coco Li 4 months, 2 weeks ago 
In the process of implementing serial gpio and adding the corresponding
ENUMs, also complete the list for npcm8xx.

Signed-off-by: Coco Li <lixiaoyan@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
---
 hw/arm/npcm8xx.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index a276fea698..10887d07fa 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -92,8 +92,14 @@ enum NPCM8xxInterrupt {
     NPCM8XX_GMAC2_IRQ,
     NPCM8XX_GMAC3_IRQ,
     NPCM8XX_GMAC4_IRQ,
-    NPCM8XX_MMC_IRQ             = 26,
+    NPCM8XX_ESPI_IRQ,
+    NPCM8XX_SIOX0_IRQ,
+    NPCM8XX_SIOX1_IRQ,
+    NPCM8XX_MC_IRQ              = 25,
+    NPCM8XX_MMC_IRQ,
     NPCM8XX_PSPI_IRQ            = 28,
+    NPCM8XX_VDMA_IRQ,
+    NPCM8XX_MCTP_IRQ,
     NPCM8XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
     NPCM8XX_TIMER1_IRQ,
     NPCM8XX_TIMER2_IRQ,
@@ -116,6 +122,14 @@ enum NPCM8xxInterrupt {
     NPCM8XX_OHCI1_IRQ,
     NPCM8XX_EHCI2_IRQ,
     NPCM8XX_OHCI2_IRQ,
+    NPCM8XX_SPI1_IRQ            = 82,
+    NPCM8XX_RNG_IRQ             = 84,
+    NPCM8XX_SPI0_IRQ            = 85,
+    NPCM8XX_SPI3_IRQ            = 87,
+    NPCM8XX_GDMA0_IRQ           = 88,
+    NPCM8XX_GDMA1_IRQ,
+    NPCM8XX_GDMA2_IRQ,
+    NPCM8XX_OTP_IRQ             = 92,
     NPCM8XX_PWM0_IRQ            = 93,   /* PWM module 0 */
     NPCM8XX_PWM1_IRQ,                   /* PWM module 1 */
     NPCM8XX_MFT0_IRQ            = 96,   /* MFT module 0 */
@@ -128,6 +142,11 @@ enum NPCM8xxInterrupt {
     NPCM8XX_MFT7_IRQ,                   /* MFT module 7 */
     NPCM8XX_PCI_MBOX1_IRQ       = 105,
     NPCM8XX_PCI_MBOX2_IRQ,
+    NPCM8XX_GPIO231_IRQ         = 108,
+    NPCM8XX_GPIO233_IRQ,
+    NPCM8XX_GPIO234_IRQ,
+    NPCM8XX_GPIO93_IRQ,
+    NPCM8XX_GPIO94_IRQ,
     NPCM8XX_GPIO0_IRQ           = 116,
     NPCM8XX_GPIO1_IRQ,
     NPCM8XX_GPIO2_IRQ,
@@ -163,6 +182,12 @@ enum NPCM8xxInterrupt {
     NPCM8XX_SMBUS24_IRQ,
     NPCM8XX_SMBUS25_IRQ,
     NPCM8XX_SMBUS26_IRQ,
+    NPCM8XX_FLM0_IRQ            = 160,
+    NPCM8XX_FLM1_IRQ,
+    NPCM8XX_FLM2_IRQ,
+    NPCM8XX_FLM3_IRQ,
+    NPCM8XX_JMT1_IRQ            = 188,
+    NPCM8XX_JMT2_IRQ,
     NPCM8XX_UART0_IRQ           = 192,
     NPCM8XX_UART1_IRQ,
     NPCM8XX_UART2_IRQ,
@@ -170,6 +195,22 @@ enum NPCM8xxInterrupt {
     NPCM8XX_UART4_IRQ,
     NPCM8XX_UART5_IRQ,
     NPCM8XX_UART6_IRQ,
+    NPCM8XX_I3C0_IRQ            = 224,
+    NPCM8XX_I3C1_IRQ,
+    NPCM8XX_I3C2_IRQ,
+    NPCM8XX_I3C3_IRQ,
+    NPCM8XX_I3C4_IRQ,
+    NPCM8XX_I3C5_IRQ,
+    NPCM8XX_A35INTERR_IRQ       = 240,
+    NPCM8XX_A35EXTERR_IRQ,
+    NPCM8XX_PMU0_IRQ,
+    NPCM8XX_PMU1_IRQ,
+    NPCM8XX_PMU2_IRQ,
+    NPCM8XX_PMU3_IRQ,
+    NPCM8XX_CTI0_IRQ,
+    NPCM8XX_CTI1_IRQ,
+    NPCM8XX_CTI2_IRQ,
+    NPCM8XX_CTI3_IRQ,
 };
 
 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
-- 
2.51.0.536.g15c5d4f767-goog
Re: [PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs
Posted by Philippe Mathieu-Daudé 4 months, 2 weeks ago 
Hi,

On 25/9/25 02:58, Coco Li wrote:
> In the process of implementing serial gpio and adding the corresponding
> ENUMs, also complete the list for npcm8xx.
> 
> Signed-off-by: Coco Li <lixiaoyan@google.com>
> Reviewed-by: Hao Wu <wuhaotsh@google.com>
> ---
>   hw/arm/npcm8xx.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
> index a276fea698..10887d07fa 100644
> --- a/hw/arm/npcm8xx.c
> +++ b/hw/arm/npcm8xx.c
> @@ -92,8 +92,14 @@ enum NPCM8xxInterrupt {
>       NPCM8XX_GMAC2_IRQ,
>       NPCM8XX_GMAC3_IRQ,
>       NPCM8XX_GMAC4_IRQ,
> -    NPCM8XX_MMC_IRQ             = 26,
> +    NPCM8XX_ESPI_IRQ,
> +    NPCM8XX_SIOX0_IRQ,
> +    NPCM8XX_SIOX1_IRQ,
> +    NPCM8XX_MC_IRQ              = 25,
> +    NPCM8XX_MMC_IRQ,
>       NPCM8XX_PSPI_IRQ            = 28,
> +    NPCM8XX_VDMA_IRQ,
> +    NPCM8XX_MCTP_IRQ,
>       NPCM8XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
>       NPCM8XX_TIMER1_IRQ,
>       NPCM8XX_TIMER2_IRQ,
> @@ -116,6 +122,14 @@ enum NPCM8xxInterrupt {
>       NPCM8XX_OHCI1_IRQ,
>       NPCM8XX_EHCI2_IRQ,
>       NPCM8XX_OHCI2_IRQ,
> +    NPCM8XX_SPI1_IRQ            = 82,
> +    NPCM8XX_RNG_IRQ             = 84,
> +    NPCM8XX_SPI0_IRQ            = 85,
> +    NPCM8XX_SPI3_IRQ            = 87,
> +    NPCM8XX_GDMA0_IRQ           = 88,
> +    NPCM8XX_GDMA1_IRQ,
> +    NPCM8XX_GDMA2_IRQ,
> +    NPCM8XX_OTP_IRQ             = 92,
>       NPCM8XX_PWM0_IRQ            = 93,   /* PWM module 0 */
>       NPCM8XX_PWM1_IRQ,                   /* PWM module 1 */
>       NPCM8XX_MFT0_IRQ            = 96,   /* MFT module 0 */
> @@ -128,6 +142,11 @@ enum NPCM8xxInterrupt {
>       NPCM8XX_MFT7_IRQ,                   /* MFT module 7 */
>       NPCM8XX_PCI_MBOX1_IRQ       = 105,
>       NPCM8XX_PCI_MBOX2_IRQ,
> +    NPCM8XX_GPIO231_IRQ         = 108,
> +    NPCM8XX_GPIO233_IRQ,
> +    NPCM8XX_GPIO234_IRQ,
> +    NPCM8XX_GPIO93_IRQ,
> +    NPCM8XX_GPIO94_IRQ,
>       NPCM8XX_GPIO0_IRQ           = 116,
>       NPCM8XX_GPIO1_IRQ,
>       NPCM8XX_GPIO2_IRQ,
> @@ -163,6 +182,12 @@ enum NPCM8xxInterrupt {
>       NPCM8XX_SMBUS24_IRQ,
>       NPCM8XX_SMBUS25_IRQ,
>       NPCM8XX_SMBUS26_IRQ,
> +    NPCM8XX_FLM0_IRQ            = 160,
> +    NPCM8XX_FLM1_IRQ,
> +    NPCM8XX_FLM2_IRQ,
> +    NPCM8XX_FLM3_IRQ,

Minor style comment, maybe worth adding a new line when the
following enum is not contiguous.

Regards,

Phil.

> +    NPCM8XX_JMT1_IRQ            = 188,
> +    NPCM8XX_JMT2_IRQ,
>       NPCM8XX_UART0_IRQ           = 192,
>       NPCM8XX_UART1_IRQ,
>       NPCM8XX_UART2_IRQ,
> @@ -170,6 +195,22 @@ enum NPCM8xxInterrupt {
>       NPCM8XX_UART4_IRQ,
>       NPCM8XX_UART5_IRQ,
>       NPCM8XX_UART6_IRQ,
> +    NPCM8XX_I3C0_IRQ            = 224,
> +    NPCM8XX_I3C1_IRQ,
> +    NPCM8XX_I3C2_IRQ,
> +    NPCM8XX_I3C3_IRQ,
> +    NPCM8XX_I3C4_IRQ,
> +    NPCM8XX_I3C5_IRQ,
> +    NPCM8XX_A35INTERR_IRQ       = 240,
> +    NPCM8XX_A35EXTERR_IRQ,
> +    NPCM8XX_PMU0_IRQ,
> +    NPCM8XX_PMU1_IRQ,
> +    NPCM8XX_PMU2_IRQ,
> +    NPCM8XX_PMU3_IRQ,
> +    NPCM8XX_CTI0_IRQ,
> +    NPCM8XX_CTI1_IRQ,
> +    NPCM8XX_CTI2_IRQ,
> +    NPCM8XX_CTI3_IRQ,
>   };
>   
>   /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
Re: [PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs
Posted by Coco Li 4 months, 2 weeks ago 
Hi Phil,

Thanks for the review!
It looks like IRQ mapping enums on other boards also generally do not have
line breaks, is it ok if I keep it like this for consistency sake?

Best,
Coco

On Wed, Sep 24, 2025 at 6:08 PM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:

> Hi,
>
> On 25/9/25 02:58, Coco Li wrote:
> > In the process of implementing serial gpio and adding the corresponding
> > ENUMs, also complete the list for npcm8xx.
> >
> > Signed-off-by: Coco Li <lixiaoyan@google.com>
> > Reviewed-by: Hao Wu <wuhaotsh@google.com>
> > ---
> >   hw/arm/npcm8xx.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 42 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
> > index a276fea698..10887d07fa 100644
> > --- a/hw/arm/npcm8xx.c
> > +++ b/hw/arm/npcm8xx.c
> > @@ -92,8 +92,14 @@ enum NPCM8xxInterrupt {
> >       NPCM8XX_GMAC2_IRQ,
> >       NPCM8XX_GMAC3_IRQ,
> >       NPCM8XX_GMAC4_IRQ,
> > -    NPCM8XX_MMC_IRQ             = 26,
> > +    NPCM8XX_ESPI_IRQ,
> > +    NPCM8XX_SIOX0_IRQ,
> > +    NPCM8XX_SIOX1_IRQ,
> > +    NPCM8XX_MC_IRQ              = 25,
> > +    NPCM8XX_MMC_IRQ,
> >       NPCM8XX_PSPI_IRQ            = 28,
> > +    NPCM8XX_VDMA_IRQ,
> > +    NPCM8XX_MCTP_IRQ,
> >       NPCM8XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
> >       NPCM8XX_TIMER1_IRQ,
> >       NPCM8XX_TIMER2_IRQ,
> > @@ -116,6 +122,14 @@ enum NPCM8xxInterrupt {
> >       NPCM8XX_OHCI1_IRQ,
> >       NPCM8XX_EHCI2_IRQ,
> >       NPCM8XX_OHCI2_IRQ,
> > +    NPCM8XX_SPI1_IRQ            = 82,
> > +    NPCM8XX_RNG_IRQ             = 84,
> > +    NPCM8XX_SPI0_IRQ            = 85,
> > +    NPCM8XX_SPI3_IRQ            = 87,
> > +    NPCM8XX_GDMA0_IRQ           = 88,
> > +    NPCM8XX_GDMA1_IRQ,
> > +    NPCM8XX_GDMA2_IRQ,
> > +    NPCM8XX_OTP_IRQ             = 92,
> >       NPCM8XX_PWM0_IRQ            = 93,   /* PWM module 0 */
> >       NPCM8XX_PWM1_IRQ,                   /* PWM module 1 */
> >       NPCM8XX_MFT0_IRQ            = 96,   /* MFT module 0 */
> > @@ -128,6 +142,11 @@ enum NPCM8xxInterrupt {
> >       NPCM8XX_MFT7_IRQ,                   /* MFT module 7 */
> >       NPCM8XX_PCI_MBOX1_IRQ       = 105,
> >       NPCM8XX_PCI_MBOX2_IRQ,
> > +    NPCM8XX_GPIO231_IRQ         = 108,
> > +    NPCM8XX_GPIO233_IRQ,
> > +    NPCM8XX_GPIO234_IRQ,
> > +    NPCM8XX_GPIO93_IRQ,
> > +    NPCM8XX_GPIO94_IRQ,
> >       NPCM8XX_GPIO0_IRQ           = 116,
> >       NPCM8XX_GPIO1_IRQ,
> >       NPCM8XX_GPIO2_IRQ,
> > @@ -163,6 +182,12 @@ enum NPCM8xxInterrupt {
> >       NPCM8XX_SMBUS24_IRQ,
> >       NPCM8XX_SMBUS25_IRQ,
> >       NPCM8XX_SMBUS26_IRQ,
> > +    NPCM8XX_FLM0_IRQ            = 160,
> > +    NPCM8XX_FLM1_IRQ,
> > +    NPCM8XX_FLM2_IRQ,
> > +    NPCM8XX_FLM3_IRQ,
>
> Minor style comment, maybe worth adding a new line when the
> following enum is not contiguous.
>
> Regards,
>
> Phil.
>
> > +    NPCM8XX_JMT1_IRQ            = 188,
> > +    NPCM8XX_JMT2_IRQ,
> >       NPCM8XX_UART0_IRQ           = 192,
> >       NPCM8XX_UART1_IRQ,
> >       NPCM8XX_UART2_IRQ,
> > @@ -170,6 +195,22 @@ enum NPCM8xxInterrupt {
> >       NPCM8XX_UART4_IRQ,
> >       NPCM8XX_UART5_IRQ,
> >       NPCM8XX_UART6_IRQ,
> > +    NPCM8XX_I3C0_IRQ            = 224,
> > +    NPCM8XX_I3C1_IRQ,
> > +    NPCM8XX_I3C2_IRQ,
> > +    NPCM8XX_I3C3_IRQ,
> > +    NPCM8XX_I3C4_IRQ,
> > +    NPCM8XX_I3C5_IRQ,
> > +    NPCM8XX_A35INTERR_IRQ       = 240,
> > +    NPCM8XX_A35EXTERR_IRQ,
> > +    NPCM8XX_PMU0_IRQ,
> > +    NPCM8XX_PMU1_IRQ,
> > +    NPCM8XX_PMU2_IRQ,
> > +    NPCM8XX_PMU3_IRQ,
> > +    NPCM8XX_CTI0_IRQ,
> > +    NPCM8XX_CTI1_IRQ,
> > +    NPCM8XX_CTI2_IRQ,
> > +    NPCM8XX_CTI3_IRQ,
> >   };
> >
> >   /* Total number of GIC interrupts, including internal Cortex-A35
> interrupts. */
>
>
Re: [PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs
Posted by Philippe Mathieu-Daudé 4 months, 1 week ago 
On 26/9/25 23:48, Coco Li wrote:
> Hi Phil,
> 
> Thanks for the review!
> It looks like IRQ mapping enums on other boards also generally do not 
> have line breaks, is it ok if I keep it like this for consistency sake?

This is just a suggestion, since you are modifying these lines. I
won't object if you keep the old style, and I don't mind if the
other boards as not changed (also, can be done as future cleanup).

(please avoid top-posting on technical mailing lists).

> 
> Best,
> Coco
> 
> On Wed, Sep 24, 2025 at 6:08 PM Philippe Mathieu-Daudé 
> <philmd@linaro.org <mailto:philmd@linaro.org>> wrote:
> 
>     Hi,
> 
>     On 25/9/25 02:58, Coco Li wrote:
>      > In the process of implementing serial gpio and adding the
>     corresponding
>      > ENUMs, also complete the list for npcm8xx.
>      >
>      > Signed-off-by: Coco Li <lixiaoyan@google.com
>     <mailto:lixiaoyan@google.com>>
>      > Reviewed-by: Hao Wu <wuhaotsh@google.com
>     <mailto:wuhaotsh@google.com>>
>      > ---
>      >   hw/arm/npcm8xx.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
>      >   1 file changed, 42 insertions(+), 1 deletion(-)
>      >
>      > diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
>      > index a276fea698..10887d07fa 100644
>      > --- a/hw/arm/npcm8xx.c
>      > +++ b/hw/arm/npcm8xx.c
>      > @@ -92,8 +92,14 @@ enum NPCM8xxInterrupt {
>      >       NPCM8XX_GMAC2_IRQ,
>      >       NPCM8XX_GMAC3_IRQ,
>      >       NPCM8XX_GMAC4_IRQ,
>      > -    NPCM8XX_MMC_IRQ             = 26,
>      > +    NPCM8XX_ESPI_IRQ,
>      > +    NPCM8XX_SIOX0_IRQ,
>      > +    NPCM8XX_SIOX1_IRQ,
>      > +    NPCM8XX_MC_IRQ              = 25,
>      > +    NPCM8XX_MMC_IRQ,
>      >       NPCM8XX_PSPI_IRQ            = 28,
>      > +    NPCM8XX_VDMA_IRQ,
>      > +    NPCM8XX_MCTP_IRQ,
>      >       NPCM8XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
>      >       NPCM8XX_TIMER1_IRQ,
>      >       NPCM8XX_TIMER2_IRQ,
>      > @@ -116,6 +122,14 @@ enum NPCM8xxInterrupt {
>      >       NPCM8XX_OHCI1_IRQ,
>      >       NPCM8XX_EHCI2_IRQ,
>      >       NPCM8XX_OHCI2_IRQ,
>      > +    NPCM8XX_SPI1_IRQ            = 82,
>      > +    NPCM8XX_RNG_IRQ             = 84,
>      > +    NPCM8XX_SPI0_IRQ            = 85,
>      > +    NPCM8XX_SPI3_IRQ            = 87,
>      > +    NPCM8XX_GDMA0_IRQ           = 88,
>      > +    NPCM8XX_GDMA1_IRQ,
>      > +    NPCM8XX_GDMA2_IRQ,
>      > +    NPCM8XX_OTP_IRQ             = 92,
>      >       NPCM8XX_PWM0_IRQ            = 93,   /* PWM module 0 */
>      >       NPCM8XX_PWM1_IRQ,                   /* PWM module 1 */
>      >       NPCM8XX_MFT0_IRQ            = 96,   /* MFT module 0 */
>      > @@ -128,6 +142,11 @@ enum NPCM8xxInterrupt {
>      >       NPCM8XX_MFT7_IRQ,                   /* MFT module 7 */
>      >       NPCM8XX_PCI_MBOX1_IRQ       = 105,
>      >       NPCM8XX_PCI_MBOX2_IRQ,
>      > +    NPCM8XX_GPIO231_IRQ         = 108,
>      > +    NPCM8XX_GPIO233_IRQ,
>      > +    NPCM8XX_GPIO234_IRQ,
>      > +    NPCM8XX_GPIO93_IRQ,
>      > +    NPCM8XX_GPIO94_IRQ,
>      >       NPCM8XX_GPIO0_IRQ           = 116,
>      >       NPCM8XX_GPIO1_IRQ,
>      >       NPCM8XX_GPIO2_IRQ,
>      > @@ -163,6 +182,12 @@ enum NPCM8xxInterrupt {
>      >       NPCM8XX_SMBUS24_IRQ,
>      >       NPCM8XX_SMBUS25_IRQ,
>      >       NPCM8XX_SMBUS26_IRQ,
>      > +    NPCM8XX_FLM0_IRQ            = 160,
>      > +    NPCM8XX_FLM1_IRQ,
>      > +    NPCM8XX_FLM2_IRQ,
>      > +    NPCM8XX_FLM3_IRQ,
> 
>     Minor style comment, maybe worth adding a new line when the
>     following enum is not contiguous.
> 
>     Regards,
> 
>     Phil.

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