[v8] riscv: Add support for MIPS P8700 CPU

[PATCH v8 02/14] target/riscv: Add cpu_set_exception_base

Posted by Djordje Todorovic 4 months, 2 weeks ago

Add a new function, so we can change reset vector from platforms
during runtime.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 14 ++++++++++++++
 target/riscv/cpu.h |  4 ++++
 2 files changed, 18 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d055ddf462..74728c5371 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -73,6 +73,20 @@ bool riscv_cpu_option_set(const char *optname)
     return g_hash_table_contains(general_user_opts, optname);
 }
 
+#ifndef CONFIG_USER_ONLY
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+    CPUState *cpu_state = qemu_get_cpu(vp_index);
+    if (cpu_state == NULL) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "cpu_set_exception_base: invalid vp_index: %u",
+                      vp_index);
+    }
+    RISCVCPU *vp = RISCV_CPU(cpu_state);
+    vp->env.resetvec = address;
+}
+#endif
+
 static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig *src)
 {
 #define BOOL_FIELD(x) dest->x |= src->x;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4a862da615..34751bd414 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -672,6 +672,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
+#ifndef CONFIG_USER_ONLY
+void cpu_set_exception_base(int vp_index, target_ulong address);
+#endif
+
 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 FIELD(TB_FLAGS, FS, 3, 2)
 /* Vector flags */
-- 
2.34.1

Re: [PATCH v8 02/14] target/riscv: Add cpu_set_exception_base

Posted by Alistair Francis 4 months, 1 week ago

On Wed, Sep 24, 2025 at 7:21 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Add a new function, so we can change reset vector from platforms
> during runtime.

There is already a "resetvec" property, which hw/riscv/opentitan.c is
using to set a custom resetvec. Why can't you use that?

Alistair

>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/cpu.c | 14 ++++++++++++++
>  target/riscv/cpu.h |  4 ++++
>  2 files changed, 18 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d055ddf462..74728c5371 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -73,6 +73,20 @@ bool riscv_cpu_option_set(const char *optname)
>      return g_hash_table_contains(general_user_opts, optname);
>  }
>
> +#ifndef CONFIG_USER_ONLY
> +void cpu_set_exception_base(int vp_index, target_ulong address)
> +{
> +    CPUState *cpu_state = qemu_get_cpu(vp_index);
> +    if (cpu_state == NULL) {
> +        qemu_log_mask(LOG_GUEST_ERROR,
> +                      "cpu_set_exception_base: invalid vp_index: %u",
> +                      vp_index);
> +    }
> +    RISCVCPU *vp = RISCV_CPU(cpu_state);
> +    vp->env.resetvec = address;
> +}
> +#endif
> +
>  static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig *src)
>  {
>  #define BOOL_FIELD(x) dest->x |= src->x;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4a862da615..34751bd414 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -672,6 +672,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
>  target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>  void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> +#ifndef CONFIG_USER_ONLY
> +void cpu_set_exception_base(int vp_index, target_ulong address);
> +#endif
> +
>  FIELD(TB_FLAGS, MEM_IDX, 0, 3)
>  FIELD(TB_FLAGS, FS, 3, 2)
>  /* Vector flags */
> --
> 2.34.1
>

Re: [PATCH v8 02/14] target/riscv: Add cpu_set_exception_base

Posted by Djordje Todorovic 4 months, 1 week ago

On 30. 9. 25. 03:06, Alistair Francis wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Wed, Sep 24, 2025 at 7:21 PM Djordje Todorovic
> <Djordje.Todorovic@htecgroup.com> wrote:
>> Add a new function, so we can change reset vector from platforms
>> during runtime.
> There is already a "resetvec" property, which hw/riscv/opentitan.c is
> using to set a custom resetvec. Why can't you use that?
>
> Alistair

Hi Alistair,

Thanks a lot for your comments!

We want to be able to change it during runtime, e.g. from

`riscv_cmgcr` added later in this patch set, so that is why we

couldn't use that property only.

Thanks,
Djordje


>> Signed-off-by: Chao-ying Fu <cfu@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>>   target/riscv/cpu.c | 14 ++++++++++++++
>>   target/riscv/cpu.h |  4 ++++
>>   2 files changed, 18 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index d055ddf462..74728c5371 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -73,6 +73,20 @@ bool riscv_cpu_option_set(const char *optname)
>>       return g_hash_table_contains(general_user_opts, optname);
>>   }
>>
>> +#ifndef CONFIG_USER_ONLY
>> +void cpu_set_exception_base(int vp_index, target_ulong address)
>> +{
>> +    CPUState *cpu_state = qemu_get_cpu(vp_index);
>> +    if (cpu_state == NULL) {
>> +        qemu_log_mask(LOG_GUEST_ERROR,
>> +                      "cpu_set_exception_base: invalid vp_index: %u",
>> +                      vp_index);
>> +    }
>> +    RISCVCPU *vp = RISCV_CPU(cpu_state);
>> +    vp->env.resetvec = address;
>> +}
>> +#endif
>> +
>>   static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig *src)
>>   {
>>   #define BOOL_FIELD(x) dest->x |= src->x;
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 4a862da615..34751bd414 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -672,6 +672,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
>>   target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>>   void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>
>> +#ifndef CONFIG_USER_ONLY
>> +void cpu_set_exception_base(int vp_index, target_ulong address);
>> +#endif
>> +
>>   FIELD(TB_FLAGS, MEM_IDX, 0, 3)
>>   FIELD(TB_FLAGS, FS, 3, 2)
>>   /* Vector flags */
>> --
>> 2.34.1
>>