[PATCH v1 0/3] Minor fixes of RISC-V CFI

Jim Shu posted 3 patches 4 months, 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250924074818.230010-1-jim.shu@sifive.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
target/riscv/csr.c                            |  2 +
target/riscv/helper.h                         |  5 ++
target/riscv/insn_trans/trans_rvzicfiss.c.inc |  9 ++++
target/riscv/op_helper.c                      | 49 +++++++++++++++++++
4 files changed, 65 insertions(+)
[PATCH v1 0/3] Minor fixes of RISC-V CFI
Posted by Jim Shu 4 months, 2 weeks ago
This patch series contains several CFI fixes:
  (1) Fix the mepc in the exception from sspopchk instruction
  (2) Fix the exception type from SSP CSR and ssamoswap instruction

Jim Shu (3):
  target/riscv: Fix the mepc when sspopchk triggers the exception
  target/riscv: Fix SSP CSR error handling in VU/VS mode
  target/riscv: Fix ssamoswap error handling

 target/riscv/csr.c                            |  2 +
 target/riscv/helper.h                         |  5 ++
 target/riscv/insn_trans/trans_rvzicfiss.c.inc |  9 ++++
 target/riscv/op_helper.c                      | 49 +++++++++++++++++++
 4 files changed, 65 insertions(+)

-- 
2.43.0
Re: [PATCH v1 0/3] Minor fixes of RISC-V CFI
Posted by Michael Tokarev 4 months ago
On 9/24/25 10:48, Jim Shu wrote:
> This patch series contains several CFI fixes:
>    (1) Fix the mepc in the exception from sspopchk instruction
>    (2) Fix the exception type from SSP CSR and ssamoswap instruction
> 
> Jim Shu (3):
>    target/riscv: Fix the mepc when sspopchk triggers the exception
>    target/riscv: Fix SSP CSR error handling in VU/VS mode
>    target/riscv: Fix ssamoswap error handling

Hi!

Is there anything in there which should be picked up for
qemu stable series (10.0.x lts and 10.1.x) ?

Thanks,

/mjt
Re: [PATCH v1 0/3] Minor fixes of RISC-V CFI
Posted by Alistair Francis 4 months ago
On Sat, Oct 4, 2025 at 5:33 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> On 9/24/25 10:48, Jim Shu wrote:
> > This patch series contains several CFI fixes:
> >    (1) Fix the mepc in the exception from sspopchk instruction
> >    (2) Fix the exception type from SSP CSR and ssamoswap instruction
> >
> > Jim Shu (3):
> >    target/riscv: Fix the mepc when sspopchk triggers the exception
> >    target/riscv: Fix SSP CSR error handling in VU/VS mode
> >    target/riscv: Fix ssamoswap error handling
>
> Hi!
>
> Is there anything in there which should be picked up for
> qemu stable series (10.0.x lts and 10.1.x) ?

If it's easy to apply then it can be applied, but it's still a very
new extension so I wouldn't worry too much about back porting the
fixes

Alistair

>
> Thanks,
>
> /mjt
>
Re: [PATCH v1 0/3] Minor fixes of RISC-V CFI
Posted by Alistair Francis 4 months, 1 week ago
On Wed, Sep 24, 2025 at 5:50 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch series contains several CFI fixes:
>   (1) Fix the mepc in the exception from sspopchk instruction
>   (2) Fix the exception type from SSP CSR and ssamoswap instruction
>
> Jim Shu (3):
>   target/riscv: Fix the mepc when sspopchk triggers the exception
>   target/riscv: Fix SSP CSR error handling in VU/VS mode
>   target/riscv: Fix ssamoswap error handling

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/csr.c                            |  2 +
>  target/riscv/helper.h                         |  5 ++
>  target/riscv/insn_trans/trans_rvzicfiss.c.inc |  9 ++++
>  target/riscv/op_helper.c                      | 49 +++++++++++++++++++
>  4 files changed, 65 insertions(+)
>
> --
> 2.43.0
>
>