Minor fixes of RISC-V CFI

[PATCH v1 0/3] Minor fixes of RISC-V CFI

Jim Shu posted 3 patches 4 days, 7 hours ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20250924074818.230010-1-jim.shu@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/csr.c                            |  2 +
target/riscv/helper.h                         |  5 ++
target/riscv/insn_trans/trans_rvzicfiss.c.inc |  9 ++++
target/riscv/op_helper.c                      | 49 +++++++++++++++++++
4 files changed, 65 insertions(+)

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[PATCH v1 0/3] Minor fixes of RISC-V CFI

Posted by Jim Shu 4 days, 7 hours ago

This patch series contains several CFI fixes:
  (1) Fix the mepc in the exception from sspopchk instruction
  (2) Fix the exception type from SSP CSR and ssamoswap instruction

Jim Shu (3):
  target/riscv: Fix the mepc when sspopchk triggers the exception
  target/riscv: Fix SSP CSR error handling in VU/VS mode
  target/riscv: Fix ssamoswap error handling

 target/riscv/csr.c                            |  2 +
 target/riscv/helper.h                         |  5 ++
 target/riscv/insn_trans/trans_rvzicfiss.c.inc |  9 ++++
 target/riscv/op_helper.c                      | 49 +++++++++++++++++++
 4 files changed, 65 insertions(+)

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2.43.0