single-binary: Make riscv cpu.h target independent

[RFC PATCH 01/34] target/riscv: Use 32 bits for misa extensions

Posted by Anton Johansson via 4 days, 8 hours ago

uint32_t is already in use in most places storing misa extensions such
as CPUArchState::misa_exts, RISCVCPUProfile::misa_exts,
RISCVImpliedExtsRule::implied_misa_exts, etc.

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/riscv/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4a862da615..a0b2ef1cc1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState;
  */
 #define RISCV_UW2_ALWAYS_STORE_AMO 1
 
-#define RV(x) ((target_ulong)1 << (x - 'A'))
+#define RV(x) ((uint32_t)1 << (x - 'A'))
 
 /*
  * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
@@ -582,7 +582,7 @@ struct RISCVCPUClass {
     RISCVCPUDef *def;
 };
 
-static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
+static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext)
 {
     return (env->misa_ext & ext) != 0;
 }
-- 
2.51.0

Re: [RFC PATCH 01/34] target/riscv: Use 32 bits for misa extensions

Posted by Philippe Mathieu-Daudé 4 days, 4 hours ago

On 24/9/25 09:20, Anton Johansson wrote:
> uint32_t is already in use in most places storing misa extensions such
> as CPUArchState::misa_exts, RISCVCPUProfile::misa_exts,
> RISCVImpliedExtsRule::implied_misa_exts, etc.

Also, the field is migrated as 32-bit:

   VMSTATE_UINT32(env.misa_ext, RISCVCPU),
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   target/riscv/cpu.h | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4a862da615..a0b2ef1cc1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState;
>    */
>   #define RISCV_UW2_ALWAYS_STORE_AMO 1
>   
> -#define RV(x) ((target_ulong)1 << (x - 'A'))
> +#define RV(x) ((uint32_t)1 << (x - 'A'))

1u, or simply using BIT():

   #define RV(x) BIT(x - 'A')

>   
>   /*
>    * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
> @@ -582,7 +582,7 @@ struct RISCVCPUClass {
>       RISCVCPUDef *def;
>   };
>   
> -static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
> +static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext)
>   {
>       return (env->misa_ext & ext) != 0;
>   }

Re: [RFC PATCH 01/34] target/riscv: Use 32 bits for misa extensions

Posted by Anton Johansson via 4 days, 2 hours ago

On 24/09/25, Philippe Mathieu-Daudé wrote:
> On 24/9/25 09:20, Anton Johansson wrote:
> > uint32_t is already in use in most places storing misa extensions such
> > as CPUArchState::misa_exts, RISCVCPUProfile::misa_exts,
> > RISCVImpliedExtsRule::implied_misa_exts, etc.
> 
> Also, the field is migrated as 32-bit:
> 
>   VMSTATE_UINT32(env.misa_ext, RISCVCPU),

Ah right!

> > 
> > Signed-off-by: Anton Johansson <anjo@rev.ng>
> > ---
> >   target/riscv/cpu.h | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 4a862da615..a0b2ef1cc1 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState;
> >    */
> >   #define RISCV_UW2_ALWAYS_STORE_AMO 1
> > -#define RV(x) ((target_ulong)1 << (x - 'A'))
> > +#define RV(x) ((uint32_t)1 << (x - 'A'))
> 
> 1u, or simply using BIT():
> 
>   #define RV(x) BIT(x - 'A')

I'll go for BIT() thanks:)