riscv: Modify minimum VLEN rule

[PATCH v2 0/2] riscv: Modify minimum VLEN rule

Max Chou posted 2 patches 5 days, 5 hours ago

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Failed in applying to current master (apply log)

target/riscv/cpu.c            |  2 +-
target/riscv/csr.c            |  3 ++-
target/riscv/machine.c        |  3 ++-
target/riscv/riscv-qmp-cmds.c |  2 +-
target/riscv/tcg/tcg-cpu.c    | 21 ++++++++++++++++++---
5 files changed, 24 insertions(+), 7 deletions(-)

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[PATCH v2 0/2] riscv: Modify minimum VLEN rule

Posted by Max Chou 5 days, 5 hours ago

According to the RISC-V unprivileged specification, the VLEN should be greater
or equal to the ELEN. This patchset provides following modifications:

* Replace the checkings of standard V with the checkings of Zve32x
* Introduces a check rule for VLEN and ELEN
* Modifies the minimum VLEN based on the vector extensions

Extension     Minimum VLEN
V                      128
Zve64[d|f|x]            64
Zve32[f|x]              32

v1: 20250627132156.440214-1-max.chou@sifive.com
- Rebase to riscv-to-apply.next branch
- Add patch 1 to replace checking RVV by checking Zve32x

Max Chou (2):
  target/riscv: rvv: Replace checking V by checking Zve32x
  target/riscv: rvv: Modify minimum VLEN according to enabled vector
    extensions

 target/riscv/cpu.c            |  2 +-
 target/riscv/csr.c            |  3 ++-
 target/riscv/machine.c        |  3 ++-
 target/riscv/riscv-qmp-cmds.c |  2 +-
 target/riscv/tcg/tcg-cpu.c    | 21 ++++++++++++++++++---
 5 files changed, 24 insertions(+), 7 deletions(-)

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2.43.0