target/riscv/cpu.c | 2 +- target/riscv/csr.c | 3 ++- target/riscv/machine.c | 3 ++- target/riscv/riscv-qmp-cmds.c | 2 +- target/riscv/tcg/tcg-cpu.c | 21 ++++++++++++++++++--- 5 files changed, 24 insertions(+), 7 deletions(-)
According to the RISC-V unprivileged specification, the VLEN should be greater
or equal to the ELEN. This patchset provides following modifications:
* Replace the checkings of standard V with the checkings of Zve32x
* Introduces a check rule for VLEN and ELEN
* Modifies the minimum VLEN based on the vector extensions
Extension Minimum VLEN
V 128
Zve64[d|f|x] 64
Zve32[f|x] 32
v1: 20250627132156.440214-1-max.chou@sifive.com
- Rebase to riscv-to-apply.next branch
- Add patch 1 to replace checking RVV by checking Zve32x
Max Chou (2):
target/riscv: rvv: Replace checking V by checking Zve32x
target/riscv: rvv: Modify minimum VLEN according to enabled vector
extensions
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 3 ++-
target/riscv/machine.c | 3 ++-
target/riscv/riscv-qmp-cmds.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 21 ++++++++++++++++++---
5 files changed, 24 insertions(+), 7 deletions(-)
--
2.43.0
On 9/23/25 12:07, Max Chou wrote: > According to the RISC-V unprivileged specification, the VLEN should be greater > or equal to the ELEN. This patchset provides following modifications: > > * Replace the checkings of standard V with the checkings of Zve32x > * Introduces a check rule for VLEN and ELEN > * Modifies the minimum VLEN based on the vector extensions > > Extension Minimum VLEN > V 128 > Zve64[d|f|x] 64 > Zve32[f|x] 32 > > v1: 20250627132156.440214-1-max.chou@sifive.com > - Rebase to riscv-to-apply.next branch > - Add patch 1 to replace checking RVV by checking Zve32x > > Max Chou (2): > target/riscv: rvv: Replace checking V by checking Zve32x > target/riscv: rvv: Modify minimum VLEN according to enabled vector > extensions Is this a qemu-stable material? (these changes does not apply directly to 10.1.x, probably the MonitorDef change in the first patch here can be dropped) Thanks, /mjt
On 10/4/25 10:44, Michael Tokarev wrote: > On 9/23/25 12:07, Max Chou wrote: >> According to the RISC-V unprivileged specification, the VLEN should be >> greater >> or equal to the ELEN. This patchset provides following modifications: >> >> * Replace the checkings of standard V with the checkings of Zve32x >> * Introduces a check rule for VLEN and ELEN >> * Modifies the minimum VLEN based on the vector extensions >> >> Extension Minimum VLEN >> V 128 >> Zve64[d|f|x] 64 >> Zve32[f|x] 32 >> >> v1: 20250627132156.440214-1-max.chou@sifive.com >> - Rebase to riscv-to-apply.next branch >> - Add patch 1 to replace checking RVV by checking Zve32x >> >> Max Chou (2): >> target/riscv: rvv: Replace checking V by checking Zve32x >> target/riscv: rvv: Modify minimum VLEN according to enabled vector >> extensions > > Is this a qemu-stable material? > (these changes does not apply directly to 10.1.x, probably the > MonitorDef change in the first patch here can be dropped) Hi! I've picked this series for qemu-stable 10.0 and 10.1 series. I still haven't received any reply from y previous email asking about these, so I'm a bit uncomfortable by picking this up for stable. But I'm releasing two stable releases today with these patches in. Thanks, /mjt
Hi Michael, Apologies for the delayed response to your question about qemu-stable. Yes, I believe this patchset is appropriate for qemu-stable material. The changes fix the VLEN minimum value to properly align with the RISC-V specification requirements (VLEN >= ELEN), which could affect the correctness of RISC-V vector extension behavior in QEMU. Thank you for picking this up for the stable 10.0 and 10.1 releases. This series is based on the riscv-to-apply.next branch (the VERSION file shows 10.1.50). Thanks, Max On Wed, Oct 8, 2025 at 3:13 PM Michael Tokarev <mjt@tls.msk.ru> wrote: > On 10/4/25 10:44, Michael Tokarev wrote: > > On 9/23/25 12:07, Max Chou wrote: > >> According to the RISC-V unprivileged specification, the VLEN should be > >> greater > >> or equal to the ELEN. This patchset provides following modifications: > >> > >> * Replace the checkings of standard V with the checkings of Zve32x > >> * Introduces a check rule for VLEN and ELEN > >> * Modifies the minimum VLEN based on the vector extensions > >> > >> Extension Minimum VLEN > >> V 128 > >> Zve64[d|f|x] 64 > >> Zve32[f|x] 32 > >> > >> v1: 20250627132156.440214-1-max.chou@sifive.com > >> - Rebase to riscv-to-apply.next branch > >> - Add patch 1 to replace checking RVV by checking Zve32x > >> > >> Max Chou (2): > >> target/riscv: rvv: Replace checking V by checking Zve32x > >> target/riscv: rvv: Modify minimum VLEN according to enabled vector > >> extensions > > > > Is this a qemu-stable material? > > (these changes does not apply directly to 10.1.x, probably the > > MonitorDef change in the first patch here can be dropped) > > Hi! > > I've picked this series for qemu-stable 10.0 and 10.1 series. > I still haven't received any reply from y previous email asking > about these, so I'm a bit uncomfortable by picking this up for > stable. But I'm releasing two stable releases today with these > patches in. > > Thanks, > > /mjt >
On Tue, Sep 23, 2025 at 7:09 PM Max Chou <max.chou@sifive.com> wrote: > > According to the RISC-V unprivileged specification, the VLEN should be greater > or equal to the ELEN. This patchset provides following modifications: > > * Replace the checkings of standard V with the checkings of Zve32x > * Introduces a check rule for VLEN and ELEN > * Modifies the minimum VLEN based on the vector extensions > > Extension Minimum VLEN > V 128 > Zve64[d|f|x] 64 > Zve32[f|x] 32 > > v1: 20250627132156.440214-1-max.chou@sifive.com > - Rebase to riscv-to-apply.next branch > - Add patch 1 to replace checking RVV by checking Zve32x > > Max Chou (2): > target/riscv: rvv: Replace checking V by checking Zve32x > target/riscv: rvv: Modify minimum VLEN according to enabled vector > extensions Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 2 +- > target/riscv/csr.c | 3 ++- > target/riscv/machine.c | 3 ++- > target/riscv/riscv-qmp-cmds.c | 2 +- > target/riscv/tcg/tcg-cpu.c | 21 ++++++++++++++++++--- > 5 files changed, 24 insertions(+), 7 deletions(-) > > -- > 2.43.0 > >
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