[v5] Add IBM PPE42 CPU support

[PATCH v5 5/9] target/ppc: Support for IBM PPE42 MMU

Posted by Glenn Miles 1 month, 3 weeks ago

The IBM PPE42 processor only supports real mode
addressing and does not distinguish between
problem and supervisor states. It also uses
the IR and DR MSR bits for other purposes.
Therefore, add a check for PPE42 when we update
hflags and cause it to ignore the IR and DR bits
when calculating MMU indexes.

Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
---
 target/ppc/helper_regs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 41b7b939ec..a07e6a7b7b 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -186,6 +186,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
     if (env->spr[SPR_LPCR] & LPCR_HR) {
         hflags |= 1 << HFLAGS_HR;
     }
+    if (unlikely(ppc_flags & POWERPC_FLAG_PPE42)) {
+        /* PPE42 has a single address space and no problem state */
+        msr = 0;
+    }
 
 #ifndef CONFIG_USER_ONLY
     if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
-- 
2.43.0

Re: [PATCH v5 5/9] target/ppc: Support for IBM PPE42 MMU

Posted by Chinmay Rath 1 month, 2 weeks ago

On 9/18/25 23:57, Glenn Miles wrote:
> The IBM PPE42 processor only supports real mode
> addressing and does not distinguish between
> problem and supervisor states. It also uses
> the IR and DR MSR bits for other purposes.
> Therefore, add a check for PPE42 when we update
> hflags and cause it to ignore the IR and DR bits
> when calculating MMU indexes.
>
> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
> ---
>   target/ppc/helper_regs.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
> index 41b7b939ec..a07e6a7b7b 100644
> --- a/target/ppc/helper_regs.c
> +++ b/target/ppc/helper_regs.c
> @@ -186,6 +186,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
>       if (env->spr[SPR_LPCR] & LPCR_HR) {
>           hflags |= 1 << HFLAGS_HR;
>       }
> +    if (unlikely(ppc_flags & POWERPC_FLAG_PPE42)) {
> +        /* PPE42 has a single address space and no problem state */
> +        msr = 0;
> +    }
>   
>   #ifndef CONFIG_USER_ONLY
>       if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {