[v2] target/riscv: Implement Smsdid and Smmpt extension

[PATCH v2 0/6] target/riscv: Implement Smsdid and Smmpt extension

LIU Zhiwei posted 6 patches 1 month, 3 weeks ago

Diff against v3 v4
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250918061911.904-1-zhiwei._5Fliu@linux.alibaba.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c                            |   6 +-
target/riscv/cpu.h                            |   9 +-
target/riscv/cpu_bits.h                       |  27 ++
target/riscv/cpu_cfg_fields.h.inc             |   2 +
target/riscv/cpu_helper.c                     |  81 +++++-
target/riscv/csr.c                            |  95 ++++++
target/riscv/insn32.decode                    |   2 +
.../riscv/insn_trans/trans_privileged.c.inc   |  30 ++
target/riscv/meson.build                      |   1 +
target/riscv/pmp.h                            |   3 +
target/riscv/riscv_smmpt.c                    | 274 ++++++++++++++++++
target/riscv/riscv_smmpt.h                    |  36 +++
12 files changed, 560 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/riscv_smmpt.c
create mode 100644 target/riscv/riscv_smmpt.h

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[PATCH v2 0/6] target/riscv: Implement Smsdid and Smmpt extension

Posted by LIU Zhiwei 1 month, 3 weeks ago

This patch set introduces support for the RISC-V Smmpt (Supervisor
Memory-tracking and Protection Table) extension. Smmpt provides a
hardware mechanism for fine-grained memory protection, checked after
address translation, which is particularly useful for supervisor-level
sandboxing and security monitoring.

The rfc patch set:
https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html

rfc->v2:
    1. When ext_smmpt is false or BARE mode, make other fields in mmpt
       CSR zero.
    2. Add patch 5 to fix smrnmi ISA string order.
    3. Fix patch 6 smmpt and smsdid ISA string order.
    4. Make smmpt and smsdid experiment extensions.
    5. Add review tags.

LIU Zhiwei (6):
  target/riscv: Add basic definitions and CSRs for SMMPT
  target/riscv: Implement core SMMPT lookup logic
  target/riscv: Integrate SMMPT checks into MMU and TLB fill
  target/riscv: Implement SMMPT fence instructions
  target/riscv: Fix smrnmi isa alphabetical order
  target/riscv: Enable SMMPT extension

 target/riscv/cpu.c                            |   6 +-
 target/riscv/cpu.h                            |   9 +-
 target/riscv/cpu_bits.h                       |  27 ++
 target/riscv/cpu_cfg_fields.h.inc             |   2 +
 target/riscv/cpu_helper.c                     |  81 +++++-
 target/riscv/csr.c                            |  95 ++++++
 target/riscv/insn32.decode                    |   2 +
 .../riscv/insn_trans/trans_privileged.c.inc   |  30 ++
 target/riscv/meson.build                      |   1 +
 target/riscv/pmp.h                            |   3 +
 target/riscv/riscv_smmpt.c                    | 274 ++++++++++++++++++
 target/riscv/riscv_smmpt.h                    |  36 +++
 12 files changed, 560 insertions(+), 6 deletions(-)
 create mode 100644 target/riscv/riscv_smmpt.c
 create mode 100644 target/riscv/riscv_smmpt.h

-- 
2.25.1

Re: [PATCH v2 0/6] target/riscv: Implement Smsdid and Smmpt extension

Posted by Alistair Francis 2 days, 20 hours ago

On Thu, Sep 18, 2025 at 4:20 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> This patch set introduces support for the RISC-V Smmpt (Supervisor
> Memory-tracking and Protection Table) extension. Smmpt provides a
> hardware mechanism for fine-grained memory protection, checked after
> address translation, which is particularly useful for supervisor-level
> sandboxing and security monitoring.
>
> The rfc patch set:
> https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
>
> rfc->v2:
>     1. When ext_smmpt is false or BARE mode, make other fields in mmpt
>        CSR zero.
>     2. Add patch 5 to fix smrnmi ISA string order.
>     3. Fix patch 6 smmpt and smsdid ISA string order.
>     4. Make smmpt and smsdid experiment extensions.
>     5. Add review tags.
>
> LIU Zhiwei (6):
>   target/riscv: Add basic definitions and CSRs for SMMPT
>   target/riscv: Implement core SMMPT lookup logic
>   target/riscv: Integrate SMMPT checks into MMU and TLB fill
>   target/riscv: Implement SMMPT fence instructions
>   target/riscv: Fix smrnmi isa alphabetical order
>   target/riscv: Enable SMMPT extension

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                            |   6 +-
>  target/riscv/cpu.h                            |   9 +-
>  target/riscv/cpu_bits.h                       |  27 ++
>  target/riscv/cpu_cfg_fields.h.inc             |   2 +
>  target/riscv/cpu_helper.c                     |  81 +++++-
>  target/riscv/csr.c                            |  95 ++++++
>  target/riscv/insn32.decode                    |   2 +
>  .../riscv/insn_trans/trans_privileged.c.inc   |  30 ++
>  target/riscv/meson.build                      |   1 +
>  target/riscv/pmp.h                            |   3 +
>  target/riscv/riscv_smmpt.c                    | 274 ++++++++++++++++++
>  target/riscv/riscv_smmpt.h                    |  36 +++
>  12 files changed, 560 insertions(+), 6 deletions(-)
>  create mode 100644 target/riscv/riscv_smmpt.c
>  create mode 100644 target/riscv/riscv_smmpt.h
>
> --
> 2.25.1
>
>