[v3] Support PCIe RC to AST2600 and AST2700

[PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700

Posted by Jamin Lin via 1 month, 3 weeks ago

v1:
 1. Add PCIe PHY, CFG, and MMIO window support for AST2600.
    Note: Only supports RC_H.
 2. Add PCIe PHY, CFG, and MMIO window support for AST2700.
    Note: Supports 3 RCs.

v2:
  1. Introduce a new root port device.
  2. For AST2600 RC_H, add the root device at 80:00.0 and a root port at 80.08.0 
     to match the real hardware topology, allowing users to attach PCIe devices 
     at the root port.
  3. For AST2700, add a root port at 00.00.0 for each PCIe root complex to match
     the real hardware topology, allowing users to attach PCIe devices at the
     root port.

v3:
  1. Fix review issues.
  2. update functional test for the e1000e network card.
  3. update license header
  4. Adding "Based on previous work from Cedric Le Goater, with Jamin's summary
     implementation.

Dependencies

QEMU version:
https://github.com/qemu/qemu/commit/f0007b7f03e2d7fc33e71c3a582f2364c51a226b

This patch series depends on the following patch series:
1. hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb
https://patchwork.kernel.org/project/qemu-devel/patch/20250902062550.3797040-1-jamin_lin@aspeedtech.com/
2. tests/functional/arm: Update test images for ASPEED chips
https://patchwork.kernel.org/project/qemu-devel/cover/20250904100556.1729604-1-kane_chen@aspeedtech.com/
3. tests/functional/arm: Add OTP functional test 
https://patchwork.kernel.org/project/qemu-devel/cover/20250917035917.4141723-1-kane_chen@aspeedtech.com/

Testing the PCIe Root Complex model with the e1000e PCIe device

AST2600 test environment
Test image: ASPEED SDK v09.07
Download
https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.07/ast2600-default-obmc.tar.gz

When booted, lspci should show one root device at 80:00.0 and a root
port at 80:08.0, matching the expected hardware topology:

```
root@ast2600-default:~# lspci
80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600
80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
```

The e1000e driver is included in this image. Attach the e1000e device on
bus pcie.0 with the following command line:

```
 -device e1000e,netdev=net0,bus=pcie.0 \
 -netdev user,id=net0,hostfwd=:127.0.0.1:3222-:22,hostname=qemu0 \
```

After boot, lspci should show the e1000e device enumerated at 81:00.0:

```
root@ast2600-default:~# lspci
80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600
80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
```

The e1000e driver should probe successfully, and a new Ethernet interface
should appear:

```
root@ast2600-default:~# ifconfig
eth4      Link encap:Ethernet  HWaddr 52:54:00:12:34:5A
          inet addr:10.0.2.15  Bcast:10.0.2.255  Mask:255.255.255.0
          inet6 addr: fe80::5054:ff:fe12:345a/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:25 errors:0 dropped:0 overruns:0 frame:0
          TX packets:57 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:5524 (5.3 KiB)  TX bytes:8488 (8.2 KiB)
          Interrupt:81 Memory:70040000-70060000
```
          
AST2700 test environment
Test image: ASPEED SDK v09.07
Download
https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.07/ast2700-default-obmc.tar.gz

By default, the ASPEED SDK only enables PCIe root complex 2 (RC2). If you
want to test all three PCIe root complexes, please use the customized
image provided here:
 https://github.com/jamin-aspeed/openbmc/releases/download/qemu-test-0907/ast2700-default-pcie-qemu.tar.xz

When booted, lspci should show one root port at 00:00.0 on the
pcie.2 bus. The domain for PCIe RC2 is 0002, which matches the
expected hardware topology:

```
root@ast2700-default:~# lspci
0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
```

The e1000e driver is included in this image. Attach the e1000e device to
bus pcie.2 using the following command line:

```
 -device e1000e,netdev=net0,bus=pcie.2 \
 -netdev user,id=net0,hostfwd=:127.0.0.1:3222-:22,hostname=qemu0 \
```

After boot, lspci should show the e1000e device enumerated at
0002:01:00.0:

```
root@ast2700-default:~# lspci
0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
0002:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
```

The e1000e driver should probe successfully, and a new Ethernet interface
should appear:

```
root@ast2700-default:~# ifconfig
eth2      Link encap:Ethernet  HWaddr 52:54:00:12:34:56
          inet addr:10.0.2.15  Bcast:10.0.2.255  Mask:255.255.255.0
          inet6 addr: fe80::5054:ff:fe12:3456/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:21 errors:0 dropped:0 overruns:0 frame:0
          TX packets:48 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:5388 (5.2 KiB)  TX bytes:8244 (8.0 KiB)
          Interrupt:42 Memory:a0040000-a0060000
```          

Jamin Lin (14):
  hw/pci/pci_ids: Add PCI vendor ID for ASPEED
  hw/pci-host/aspeed: Add AST2600 PCIe PHY model
  hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge
  hw/pci-host/aspeed: Add AST2600 PCIe Root Device support
  hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address
    configurable
  hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
  hw/arm/aspeed: Wire up PCIe devices in SoC model
  hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)
  hw/pci-host/aspeed: Add AST2700 PCIe PHY
  hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks
  hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0
    to AST2700
  hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700
  tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test
  tests/functional/aarch64/aspeed_ast2700: Add PCIe and network tests

 include/hw/arm/aspeed_soc.h                   |   14 +
 include/hw/pci-host/aspeed_pcie.h             |  137 +++
 include/hw/pci/pci_ids.h                      |    2 +
 hw/arm/aspeed_ast2600.c                       |   79 ++
 hw/arm/aspeed_ast27x0.c                       |   76 ++
 hw/pci-host/aspeed_pcie.c                     | 1009 +++++++++++++++++
 hw/arm/Kconfig                                |    3 +
 hw/pci-host/Kconfig                           |    4 +
 hw/pci-host/meson.build                       |    1 +
 hw/pci-host/trace-events                      |   11 +
 .../functional/aarch64/test_aspeed_ast2700.py |   19 +
 .../aarch64/test_aspeed_ast2700fc.py          |   13 +
 tests/functional/arm/test_aspeed_ast2600.py   |   20 +
 13 files changed, 1388 insertions(+)
 create mode 100644 include/hw/pci-host/aspeed_pcie.h
 create mode 100644 hw/pci-host/aspeed_pcie.c

-- 
2.43.0

Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700

Posted by Cédric Le Goater 1 month, 3 weeks ago

Hell Jamin,

On 9/18/25 05:13, Jamin Lin wrote:
> v1:
>   1. Add PCIe PHY, CFG, and MMIO window support for AST2600.
>      Note: Only supports RC_H.
>   2. Add PCIe PHY, CFG, and MMIO window support for AST2700.
>      Note: Supports 3 RCs.
> 
> v2:
>    1. Introduce a new root port device.
>    2. For AST2600 RC_H, add the root device at 80:00.0 and a root port at 80.08.0
>       to match the real hardware topology, allowing users to attach PCIe devices
>       at the root port.
>    3. For AST2700, add a root port at 00.00.0 for each PCIe root complex to match
>       the real hardware topology, allowing users to attach PCIe devices at the
>       root port.
> 
> v3:
>    1. Fix review issues.
>    2. update functional test for the e1000e network card.
>    3. update license header
>    4. Adding "Based on previous work from Cedric Le Goater, with Jamin's summary
>       implementation.

v3 looks good. I only had a few comments on memory allocation
(g_autofree and MMIO alias regions) and on functional tests.

v4 should be the last.


> 
> Dependencies
> 
> QEMU version:
> https://github.com/qemu/qemu/commit/f0007b7f03e2d7fc33e71c3a582f2364c51a226b
> 
> This patch series depends on the following patch series:
> 1. hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb
> https://patchwork.kernel.org/project/qemu-devel/patch/20250902062550.3797040-1-jamin_lin@aspeedtech.com/
> 2. tests/functional/arm: Update test images for ASPEED chips
> https://patchwork.kernel.org/project/qemu-devel/cover/20250904100556.1729604-1-kane_chen@aspeedtech.com/
> 3. tests/functional/arm: Add OTP functional test
> https://patchwork.kernel.org/project/qemu-devel/cover/20250917035917.4141723-1-kane_chen@aspeedtech.com/


There changes are in aspeed-next. You could use it as a reference
in the cover letter.


Thanks,

C.

RE: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700

Posted by Jamin Lin 1 month, 3 weeks ago

Hi Cédric

> Subject: Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and
> AST2700
> 
> Hell Jamin,
> 
> On 9/18/25 05:13, Jamin Lin wrote:
> > v1:
> >   1. Add PCIe PHY, CFG, and MMIO window support for AST2600.
> >      Note: Only supports RC_H.
> >   2. Add PCIe PHY, CFG, and MMIO window support for AST2700.
> >      Note: Supports 3 RCs.
> >
> > v2:
> >    1. Introduce a new root port device.
> >    2. For AST2600 RC_H, add the root device at 80:00.0 and a root port at
> 80.08.0
> >       to match the real hardware topology, allowing users to attach PCIe
> devices
> >       at the root port.
> >    3. For AST2700, add a root port at 00.00.0 for each PCIe root complex to
> match
> >       the real hardware topology, allowing users to attach PCIe devices at
> the
> >       root port.
> >
> > v3:
> >    1. Fix review issues.
> >    2. update functional test for the e1000e network card.
> >    3. update license header
> >    4. Adding "Based on previous work from Cedric Le Goater, with Jamin's
> summary
> >       implementation.
> 
> v3 looks good. I only had a few comments on memory allocation (g_autofree
> and MMIO alias regions) and on functional tests.
> 
> v4 should be the last.
> 

Thanks for your review and kindly support.
Will resend v4 very soon.
 
> 
> >
> > Dependencies
> >
> > QEMU version:
> >
> https://github.com/qemu/qemu/commit/f0007b7f03e2d7fc33e71c3a582f2364
> c5
> > 1a226b
> >
> > This patch series depends on the following patch series:
> > 1. hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb
> > https://patchwork.kernel.org/project/qemu-devel/patch/20250902062550.3
> > 797040-1-jamin_lin@aspeedtech.com/
> > 2. tests/functional/arm: Update test images for ASPEED chips
> > https://patchwork.kernel.org/project/qemu-devel/cover/20250904100556.1
> > 729604-1-kane_chen@aspeedtech.com/
> > 3. tests/functional/arm: Add OTP functional test
> > https://patchwork.kernel.org/project/qemu-devel/cover/20250917035917.4
> > 141723-1-kane_chen@aspeedtech.com/
> 
> 
> There changes are in aspeed-next. You could use it as a reference in the cover
> letter.
> 
Will update it in v4 cover letter.

Jamin
> 
> Thanks,
> 
> C.

Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700

Posted by Cédric Le Goater 1 month, 3 weeks ago

On 9/18/25 11:08, Jamin Lin wrote:
> Hi Cédric
> 
>> Subject: Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and
>> AST2700
>>
>> Hell Jamin,
>>
>> On 9/18/25 05:13, Jamin Lin wrote:
>>> v1:
>>>    1. Add PCIe PHY, CFG, and MMIO window support for AST2600.
>>>       Note: Only supports RC_H.
>>>    2. Add PCIe PHY, CFG, and MMIO window support for AST2700.
>>>       Note: Supports 3 RCs.
>>>
>>> v2:
>>>     1. Introduce a new root port device.
>>>     2. For AST2600 RC_H, add the root device at 80:00.0 and a root port at
>> 80.08.0
>>>        to match the real hardware topology, allowing users to attach PCIe
>> devices
>>>        at the root port.
>>>     3. For AST2700, add a root port at 00.00.0 for each PCIe root complex to
>> match
>>>        the real hardware topology, allowing users to attach PCIe devices at
>> the
>>>        root port.
>>>
>>> v3:
>>>     1. Fix review issues.
>>>     2. update functional test for the e1000e network card.
>>>     3. update license header
>>>     4. Adding "Based on previous work from Cedric Le Goater, with Jamin's
>> summary
>>>        implementation.
>>
>> v3 looks good. I only had a few comments on memory allocation (g_autofree
>> and MMIO alias regions) and on functional tests.
>>
>> v4 should be the last.
>>
> 
> Thanks for your review and kindly support.
> Will resend v4 very soon.

One last thing, the list of PCI capabilities reported on real HW
is a little different. See below. When you have time, it would
be good to adjust the model if possible. It can come later.


Thanks,

C.



root@ast2600-default:~# lspci -vvv
80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600
	Subsystem: ASPEED Technology, Inc. Device 2600
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0

80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge (rev 06) (prog-if 00 [Normal decode])
	Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 82
	Bus: primary=80, secondary=81, subordinate=81, sec-latency=0
	I/O behind bridge: 1000-1fff [size=4K] [16-bit]
	Memory behind bridge: 70000000-700fffff [size=1M] [32-bit]
	Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff [disabled] [64-bit]
	Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity+ SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
		Address: 000000001e77005c  Data: 0000
	Capabilities: [78] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [80] Express (v2) Root Port (Slot-), IntMsgNum 0
		DevCap:	MaxPayload 512 bytes, PhantFunc 0
			ExtTag+ RBE+ TEE-IO-
		DevCtl:	CorrErr- NonFatalErr- FatalErr- UnsupReq-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <64us
			ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk-
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1
			TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		RootCap: CRSVisible-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR-
			 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
			 EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
			 FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- ARIFwd-
			 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd-
			 AtomicOpsCtl: ReqEn- EgressBlck-
			 IDOReq- IDOCompl- LTR- EmergencyPowerReductionReq-
			 10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete- EqualizationPhase1-
			 EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest-
			 Retimer- 2Retimers- CrosslinkRes: unsupported
	Capabilities: [c0] Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed- WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
			Status:	NegoPending- InProgress-
	Capabilities: [800 v1] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP-
			ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr-
			PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP-
			ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr-
			PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+
			ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr-
			PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrIntErr- HeaderOF-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr- HeaderOF-
		AERCap:	First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
			MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
		HeaderLog: 00000000 00000000 00000000 00000000
		RootCmd: CERptEn- NFERptEn- FERptEn-
		RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
			 FirstFatal- NonFatalMsg- FatalMsg- IntMsgNum 0
		ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
	Kernel driver in use: pcieport

RE: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700

Posted by Jamin Lin 1 month, 3 weeks ago

Hi Cédric

> Subject: Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and
> AST2700
> 
> On 9/18/25 11:08, Jamin Lin wrote:
> > Hi Cédric
> >
> >> Subject: Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and
> >> AST2700
> >>
> >> Hell Jamin,
> >>
> >> On 9/18/25 05:13, Jamin Lin wrote:
> >>> v1:
> >>>    1. Add PCIe PHY, CFG, and MMIO window support for AST2600.
> >>>       Note: Only supports RC_H.
> >>>    2. Add PCIe PHY, CFG, and MMIO window support for AST2700.
> >>>       Note: Supports 3 RCs.
> >>>
> >>> v2:
> >>>     1. Introduce a new root port device.
> >>>     2. For AST2600 RC_H, add the root device at 80:00.0 and a root
> >>> port at
> >> 80.08.0
> >>>        to match the real hardware topology, allowing users to attach
> >>> PCIe
> >> devices
> >>>        at the root port.
> >>>     3. For AST2700, add a root port at 00.00.0 for each PCIe root
> >>> complex to
> >> match
> >>>        the real hardware topology, allowing users to attach PCIe
> >>> devices at
> >> the
> >>>        root port.
> >>>
> >>> v3:
> >>>     1. Fix review issues.
> >>>     2. update functional test for the e1000e network card.
> >>>     3. update license header
> >>>     4. Adding "Based on previous work from Cedric Le Goater, with
> >>> Jamin's
> >> summary
> >>>        implementation.
> >>
> >> v3 looks good. I only had a few comments on memory allocation
> >> (g_autofree and MMIO alias regions) and on functional tests.
> >>
> >> v4 should be the last.
> >>
> >
> > Thanks for your review and kindly support.
> > Will resend v4 very soon.
> 
> One last thing, the list of PCI capabilities reported on real HW is a little
> different. See below. When you have time, it would be good to adjust the
> model if possible. It can come later.
> 

Thanks for the suggestion and for reporting this issue. I’ll add it to my working queue.
Here are the tasks currently in my queue:

1. Control coprocessor reset for AST2700
https://patchwork.kernel.org/project/qemu-devel/cover/20250717034054.1903991-1-jamin_lin@aspeedtech.com/
2. Analyze issue "func-arm-aspeed_ast2500 test occasionally times out"
https://gitlab.com/qemu-project/qemu/-/issues/3117
3. Adjust PCIe capabilities
3. Support AST2700 IPC model(may require refactoring the INTC model if needed)
4. Support AST2700 A2 (planned for end of this year or Q1 next year) 
5. Support AST2700 boot from BootMCU(RISC-V) instead of vbootrom, if a single binary ready.

Thanks-Jamin

> 
> Thanks,
> 
> C.
> 
> 
> 
> root@ast2600-default:~# lspci -vvv
> 80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600
> 	Subsystem: ASPEED Technology, Inc. Device 2600
> 	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx-
> 	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> 	Latency: 0
> 
> 80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge (rev 06)
> (prog-if 00 [Normal decode])
> 	Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
> 	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr+ Stepping- SERR+ FastB2B- DisINTx+
> 	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> 	Latency: 0, Cache Line Size: 64 bytes
> 	Interrupt: pin A routed to IRQ 82
> 	Bus: primary=80, secondary=81, subordinate=81, sec-latency=0
> 	I/O behind bridge: 1000-1fff [size=4K] [16-bit]
> 	Memory behind bridge: 70000000-700fffff [size=1M] [32-bit]
> 	Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
> [disabled] [64-bit]
> 	Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort+ <SERR- <PERR-
> 	BridgeCtl: Parity+ SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-
> 		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> 	Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
> 		Address: 000000001e77005c  Data: 0000
> 	Capabilities: [78] Power Management version 3
> 		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA
> PME(D0+,D1+,D2+,D3hot+,D3cold+)
> 		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
> 	Capabilities: [80] Express (v2) Root Port (Slot-), IntMsgNum 0
> 		DevCap:	MaxPayload 512 bytes, PhantFunc 0
> 			ExtTag+ RBE+ TEE-IO-
> 		DevCtl:	CorrErr- NonFatalErr- FatalErr- UnsupReq-
> 			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
> 			MaxPayload 128 bytes, MaxReadReq 512 bytes
> 		DevSta:	CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+
> TransPend-
> 		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency
> L0s <1us, L1 <64us
> 			ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+
> 		LnkCtl:	ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk-
> 			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> 		LnkSta:	Speed 2.5GT/s, Width x1
> 			TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
> 		RootCap: CRSVisible-
> 		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+
> CRSVisible-
> 		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
> 		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+
> NROPrPrP- LTR-
> 			 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt-
> EETLPPrefix-
> 			 EmergencyPowerReduction Not Supported,
> EmergencyPowerReductionInit-
> 			 FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp-
> ARIFwd-
> 			 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
> 		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd-
> 			 AtomicOpsCtl: ReqEn- EgressBlck-
> 			 IDOReq- IDOCompl- LTR- EmergencyPowerReductionReq-
> 			 10BitTagReq- OBFF Disabled, EETLPPrefixBlk-
> 		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
> 			 Transmit Margin: Normal Operating Range,
> EnterModifiedCompliance- ComplianceSOS-
> 			 Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB
> preshoot
> 		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-
> EqualizationPhase1-
> 			 EqualizationPhase2- EqualizationPhase3-
> LinkEqualizationRequest-
> 			 Retimer- 2Retimers- CrosslinkRes: unsupported
> 	Capabilities: [c0] Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI
> Bridge
> 	Capabilities: [100 v1] Virtual Channel
> 		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
> 		Arb:	Fixed- WRR32- WRR64- WRR128-
> 		Ctrl:	ArbSelect=Fixed
> 		Status:	InProgress-
> 		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
> 			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
> 			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
> 			Status:	NegoPending- InProgress-
> 	Capabilities: [800 v1] Advanced Error Reporting
> 		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt-
> RxOF- MalfTLP-
> 			ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP-
> AtomicOpBlocked- TLPBlockedErr-
> 			PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP-
> PCRC_CHECK- TLPXlatBlocked-
> 		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt-
> RxOF- MalfTLP-
> 			ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP-
> AtomicOpBlocked- TLPBlockedErr-
> 			PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP-
> PCRC_CHECK- TLPXlatBlocked-
> 		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt-
> RxOF+ MalfTLP+
> 			ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP-
> AtomicOpBlocked- TLPBlockedErr-
> 			PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP-
> PCRC_CHECK- TLPXlatBlocked-
> 		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout-
> AdvNonFatalErr- CorrIntErr- HeaderOF-
> 		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout-
> AdvNonFatalErr+ CorrIntErr- HeaderOF-
> 		AERCap:	First Error Pointer: 00, ECRCGenCap- ECRCGenEn-
> ECRCChkCap- ECRCChkEn-
> 			MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
> 		HeaderLog: 00000000 00000000 00000000 00000000
> 		RootCmd: CERptEn- NFERptEn- FERptEn-
> 		RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
> 			 FirstFatal- NonFatalMsg- FatalMsg- IntMsgNum 0
> 		ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
> 	Kernel driver in use: pcieport
> 
>

Aspeed backlog (was Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700)

Posted by Cédric Le Goater 1 month, 3 weeks ago

Hello Jamin,

>> One last thing, the list of PCI capabilities reported on real HW is a little
>> different. See below. When you have time, it would be good to adjust the
>> model if possible. It can come later.
>>
> 
> Thanks for the suggestion and for reporting this issue. I’ll add it to my working queue.
> Here are the tasks currently in my queue:
> 
> 1. Control coprocessor reset for AST2700
> https://patchwork.kernel.org/project/qemu-devel/cover/20250717034054.1903991-1-jamin_lin@aspeedtech.com/

This needs a rework of the co processor models. This should be QEMU 10.2
material IMO.

> 2. Analyze issue "func-arm-aspeed_ast2500 test occasionally times out"
> https://gitlab.com/qemu-project/qemu/-/issues/3117
> 3. Adjust PCIe capabilities
> 3. Support AST2700 IPC model(may require refactoring the INTC model if needed)
> 4. Support AST2700 A2 (planned for end of this year or Q1 next year)
> 5. Support AST2700 boot from BootMCU(RISC-V) instead of vbootrom, if a single binary ready.

It would be great if Troy (?) could resend the models, it's good to have
since single binary is making progress.



Also, these changes may be of interest, they need review :

   - usb/uhci: Add UHCI sysbus support, and enable for AST (Guenter Roeck)
     https://lore.kernel.org//qemu-devel/20241112170152.217664-1-linux@roeck-us.net

     Looks really good. Needs reviewers and stakeholders.

   - i3c: aspeed: Add I3C support (Joe Komlodi)
     https://lore.kernel.org//qemu-devel/20250613000411.1516521-1-komlodi@google.com

     Looks good overall. Needs reviewers and stakeholders.

   - Add Aspeed GPIO test and Support Nuvoton Serial GPIO (Coco Li)
     https://lore.kernel.org//qemu-devel/20250903213809.3779860-1-lixiaoyan@google.com

     Needs reviewers

   - hw/arm/aspeed: AST1700 IO expander support for (Kane-Chen-AS)
     https://lore.kernel.org//qemu-devel/20250917013143.1600377-1-kane_chen@aspeedtech.com

     Needs rework. I will comment more when time permits
     

Thanks,

C.

RE: Aspeed backlog (was Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and AST2700)

Posted by Jamin Lin 1 month, 3 weeks ago

Hi Cédric

> Subject: Aspeed backlog (was Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to
> AST2600 and AST2700)
> 
> Hello Jamin,
> 
> >> One last thing, the list of PCI capabilities reported on real HW is a
> >> little different. See below. When you have time, it would be good to
> >> adjust the model if possible. It can come later.
> >>
> >
> > Thanks for the suggestion and for reporting this issue. I’ll add it to my
> working queue.
> > Here are the tasks currently in my queue:
> >
> > 1. Control coprocessor reset for AST2700
> > https://patchwork.kernel.org/project/qemu-devel/cover/20250717034054.1
> > 903991-1-jamin_lin@aspeedtech.com/
> 
> This needs a rework of the co processor models. This should be QEMU 10.2
> material IMO.

Yes, I am reworking it, and I will discuss with you within this patch series if I have any questions during the rework.

> 
> > 2. Analyze issue "func-arm-aspeed_ast2500 test occasionally times out"
> > https://gitlab.com/qemu-project/qemu/-/issues/3117
> > 3. Adjust PCIe capabilities
> > 3. Support AST2700 IPC model(may require refactoring the INTC model if
> > needed) 4. Support AST2700 A2 (planned for end of this year or Q1 next
> > year) 5. Support AST2700 boot from BootMCU(RISC-V) instead of vbootrom,
> if a single binary ready.
> 
> It would be great if Troy (?) could resend the models, it's good to have since
> single binary is making progress.
> 

I will organize and send out Troy’s patch for the AST2700 BootMCU.
So far, we have only tested it up to running SPL with qemu-system-riscv32.

Thanks-Jamin
> 
> 
> Also, these changes may be of interest, they need review :
> 
>    - usb/uhci: Add UHCI sysbus support, and enable for AST (Guenter Roeck)
> 
> https://lore.kernel.org//qemu-devel/20241112170152.217664-1-linux@roeck-u
> s.net
> 
>      Looks really good. Needs reviewers and stakeholders.
> 
>    - i3c: aspeed: Add I3C support (Joe Komlodi)
> 
> https://lore.kernel.org//qemu-devel/20250613000411.1516521-1-komlodi@go
> ogle.com
> 
>      Looks good overall. Needs reviewers and stakeholders.
> 
>    - Add Aspeed GPIO test and Support Nuvoton Serial GPIO (Coco Li)
> 
> https://lore.kernel.org//qemu-devel/20250903213809.3779860-1-lixiaoyan@g
> oogle.com
> 
>      Needs reviewers
> 
>    - hw/arm/aspeed: AST1700 IO expander support for (Kane-Chen-AS)
> 
> https://lore.kernel.org//qemu-devel/20250917013143.1600377-1-kane_chen@
> aspeedtech.com
> 
>      Needs rework. I will comment more when time permits
> 
> 
> Thanks,
> 
> C.