hw/arm/xlnx-zynqmp.c | 103 +++++++++++++++++++++++++++++++---- include/hw/arm/xlnx-zynqmp.h | 5 ++ 2 files changed, 98 insertions(+), 10 deletions(-)
From: Frederic Konrad <konrad.frederic@yahoo.fr>
This wires a second GIC for the Cortex-R5, all the IRQs are split when there
is an RPU instanciated.
Signed-off-by: Clément Chigot <chigot@adacore.com>
---
Originally, this patch was member of a wider series. Other patches have
been merged since thus submit it back as a standalone patch.
https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg02328.html
---
hw/arm/xlnx-zynqmp.c | 103 +++++++++++++++++++++++++++++++----
include/hw/arm/xlnx-zynqmp.h | 5 ++
2 files changed, 98 insertions(+), 10 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index ec96a46eec..ffed6e5126 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -26,8 +26,6 @@
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
-#define GIC_NUM_SPI_INTR 160
-
#define ARM_PHYS_TIMER_PPI 30
#define ARM_VIRT_TIMER_PPI 27
#define ARM_HYP_TIMER_PPI 26
@@ -206,17 +204,26 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
- return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
+ return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
+}
+
+static unsigned int xlnx_zynqmp_get_rpu_number(MachineState *ms)
+{
+ /*
+ * RPUs will be created only if "-smp" is higher than the maximum
+ * of APUs. Round it up to 0 to avoid dealing with negative values.
+ */
+ return MAX(0, MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
+ XLNX_ZYNQMP_NUM_RPU_CPUS));
}
static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
const char *boot_cpu, Error **errp)
{
int i;
- int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
- XLNX_ZYNQMP_NUM_RPU_CPUS);
+ int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
- if (num_rpus <= 0) {
+ if (!num_rpus) {
/* Don't create rpu-cluster object if there's nothing to put in it */
return;
}
@@ -377,6 +384,7 @@ static void xlnx_zynqmp_init(Object *obj)
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
int i;
int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
+ int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
TYPE_CPU_CLUSTER);
@@ -390,6 +398,12 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize_child(obj, "gic", &s->gic, gic_class_name());
+ if (num_rpus) {
+ /* Do not create the rpu_gic if we don't have rpus */
+ object_initialize_child(obj, "rpu_gic", &s->rpu_gic,
+ gic_class_name());
+ }
+
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
object_initialize_child(obj, "gem-irq-orgate[*]",
@@ -439,6 +453,15 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize_child(obj, "qspi-irq-orgate",
&s->qspi_irq_orgate, TYPE_OR_IRQ);
+ if (num_rpus) {
+ for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
+ g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
+ object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
+ }
+ }
+
+
+
for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
}
@@ -452,9 +475,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
uint8_t i;
uint64_t ram_size;
int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
+ int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
ram_addr_t ddr_low_size, ddr_high_size;
- qemu_irq gic_spi[GIC_NUM_SPI_INTR];
+ qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
Error *err = NULL;
ram_size = memory_region_size(s->ddr_ram);
@@ -502,13 +526,22 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
g_free(ocm_name);
}
- qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq",
+ XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32);
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
qdev_prop_set_bit(DEVICE(&s->gic),
"has-virtualization-extensions", s->virt);
+ if (num_rpus) {
+ qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq",
+ XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32);
+ qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1);
+ qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus);
+ qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4);
+ }
+
qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
/* Realize APUs before realizing the GIC. KVM requires this. */
@@ -608,13 +641,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
return;
}
+ if (num_rpus) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) {
+ return;
+ }
+
+ for (i = 0; i < num_rpus; i++) {
+ qemu_irq irq;
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1,
+ GIC_BASE_ADDR + i * 0x1000);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i,
+ qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
+ ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus,
+ qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
+ ARM_CPU_FIQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 2,
+ qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
+ ARM_CPU_VIRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 3,
+ qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
+ ARM_CPU_VFIQ));
+ irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
+ arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
+ arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
+ arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
+ arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq);
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR);
+ }
+
if (!s->boot_cpu_ptr) {
error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
return;
}
- for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
- gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
+ for (i = 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) {
+ if (num_rpus) {
+ DeviceState *splitter = DEVICE(&s->splitter[i]);
+ qdev_prop_set_uint16(splitter, "num-lines", 2);
+ qdev_realize(splitter, NULL, &error_abort);
+ gic_spi[i] = qdev_get_gpio_in(splitter, 0);
+ qdev_connect_gpio_out(splitter, 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), i));
+ qdev_connect_gpio_out(splitter, 1,
+ qdev_get_gpio_in(DEVICE(&s->rpu_gic), i));
+ } else {
+ gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
+ }
}
for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index c137ac59e8..0ae00e10f6 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -42,6 +42,7 @@
#include "hw/misc/xlnx-zynqmp-crf.h"
#include "hw/timer/cadence_ttc.h"
#include "hw/usb/hcd-dwc3.h"
+#include "hw/core/split-irq.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -87,6 +88,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
#define XLNX_ZYNQMP_NUM_TTC 4
+#define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160
/*
* Unimplemented mmio regions needed to boot some images.
@@ -105,6 +107,9 @@ struct XlnxZynqMPState {
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
+ GICState rpu_gic;
+ SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
+
MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
MemoryRegion *ddr_ram;
--
2.34.1
On Mon, Sep 15, 2025 at 2:59 AM Clément Chigot <chigot@adacore.com> wrote:
> From: Frederic Konrad <konrad.frederic@yahoo.fr>
>
> This wires a second GIC for the Cortex-R5, all the IRQs are split when
> there
> is an RPU instanciated.
>
> Signed-off-by: Clément Chigot <chigot@adacore.com>
>
>
Hi!
It looks like this patch is changing multiple things, perhaps we should
split it? See inline comments.
Besides that, this looks good to me!
> ---
>
> Originally, this patch was member of a wider series. Other patches have
> been merged since thus submit it back as a standalone patch.
> https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg02328.html
>
> ---
> hw/arm/xlnx-zynqmp.c | 103 +++++++++++++++++++++++++++++++----
> include/hw/arm/xlnx-zynqmp.h | 5 ++
> 2 files changed, 98 insertions(+), 10 deletions(-)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index ec96a46eec..ffed6e5126 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -26,8 +26,6 @@
> #include "target/arm/cpu-qom.h"
> #include "target/arm/gtimer.h"
>
> -#define GIC_NUM_SPI_INTR 160
>
Could be a separate patch to use XLNX_ZYNQMP_GIC_NUM_SPI_INTR instead of
GIC_NUM_SPI_INTR?
> -
> #define ARM_PHYS_TIMER_PPI 30
> #define ARM_VIRT_TIMER_PPI 27
> #define ARM_HYP_TIMER_PPI 26
> @@ -206,17 +204,26 @@ static const XlnxZynqMPGICRegion
> xlnx_zynqmp_gic_regions[] = {
>
> static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
> {
> - return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
> + return XLNX_ZYNQMP_GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL +
> ppi_index;
> +}
> +
> +static unsigned int xlnx_zynqmp_get_rpu_number(MachineState *ms)
> +{
> + /*
> + * RPUs will be created only if "-smp" is higher than the maximum
> + * of APUs. Round it up to 0 to avoid dealing with negative values.
> + */
> + return MAX(0, MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
> + XLNX_ZYNQMP_NUM_RPU_CPUS));
>
> }
>
> static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
> const char *boot_cpu, Error **errp)
> {
> int i;
> - int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
> - XLNX_ZYNQMP_NUM_RPU_CPUS);
> + int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
>
> - if (num_rpus <= 0) {
> + if (!num_rpus) {
> /* Don't create rpu-cluster object if there's nothing to put in
> it */
> return;
> }
>
This change looks good to me but it is also a bit unrelated to wiring up a
second GIC.
> @@ -377,6 +384,7 @@ static void xlnx_zynqmp_init(Object *obj)
> XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
> int i;
> int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
> + int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
>
> object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
> TYPE_CPU_CLUSTER);
> @@ -390,6 +398,12 @@ static void xlnx_zynqmp_init(Object *obj)
>
> object_initialize_child(obj, "gic", &s->gic, gic_class_name());
>
> + if (num_rpus) {
> + /* Do not create the rpu_gic if we don't have rpus */
> + object_initialize_child(obj, "rpu_gic", &s->rpu_gic,
> + gic_class_name());
> + }
> +
> for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
> object_initialize_child(obj, "gem[*]", &s->gem[i],
> TYPE_CADENCE_GEM);
> object_initialize_child(obj, "gem-irq-orgate[*]",
> @@ -439,6 +453,15 @@ static void xlnx_zynqmp_init(Object *obj)
> object_initialize_child(obj, "qspi-irq-orgate",
> &s->qspi_irq_orgate, TYPE_OR_IRQ);
>
> + if (num_rpus) {
> + for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
> + g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
> + object_initialize_child(obj, name, &s->splitter[i],
> TYPE_SPLIT_IRQ);
> + }
> + }
> +
> +
> +
> for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
> object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
> }
> @@ -452,9 +475,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
> Error **errp)
> uint8_t i;
> uint64_t ram_size;
> int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
> + int num_rpus = xlnx_zynqmp_get_rpu_number(ms);
> const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
> ram_addr_t ddr_low_size, ddr_high_size;
> - qemu_irq gic_spi[GIC_NUM_SPI_INTR];
> + qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
> Error *err = NULL;
>
> ram_size = memory_region_size(s->ddr_ram);
> @@ -502,13 +526,22 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
> Error **errp)
> g_free(ocm_name);
> }
>
> - qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR +
> 32);
> + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq",
> + XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32);
> qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
> qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
> qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions",
> s->secure);
> qdev_prop_set_bit(DEVICE(&s->gic),
> "has-virtualization-extensions", s->virt);
>
> + if (num_rpus) {
> + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq",
> + XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32);
> + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1);
> + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus);
> + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4);
> + }
> +
> qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
>
> /* Realize APUs before realizing the GIC. KVM requires this. */
> @@ -608,13 +641,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
> Error **errp)
> return;
> }
>
> + if (num_rpus) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) {
> + return;
> + }
> +
> + for (i = 0; i < num_rpus; i++) {
> + qemu_irq irq;
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1,
> + GIC_BASE_ADDR + i * 0x1000);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i,
> + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
> + ARM_CPU_IRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus,
> + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
> + ARM_CPU_FIQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus
> * 2,
> + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
> + ARM_CPU_VIRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus
> * 3,
> + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]),
> + ARM_CPU_VFIQ));
> + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
> + arm_gic_ppi_index(i,
> ARM_PHYS_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS,
> irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
> + arm_gic_ppi_index(i,
> ARM_VIRT_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT,
> irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
> + arm_gic_ppi_index(i,
> ARM_HYP_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP,
> irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic),
> + arm_gic_ppi_index(i,
> ARM_SEC_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC,
> irq);
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR);
> + }
> +
> if (!s->boot_cpu_ptr) {
> error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
> return;
> }
>
> - for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
> - gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
> + for (i = 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) {
> + if (num_rpus) {
> + DeviceState *splitter = DEVICE(&s->splitter[i]);
> + qdev_prop_set_uint16(splitter, "num-lines", 2);
> + qdev_realize(splitter, NULL, &error_abort);
> + gic_spi[i] = qdev_get_gpio_in(splitter, 0);
> + qdev_connect_gpio_out(splitter, 0,
> + qdev_get_gpio_in(DEVICE(&s->gic), i));
> + qdev_connect_gpio_out(splitter, 1,
> + qdev_get_gpio_in(DEVICE(&s->rpu_gic),
> i));
> + } else {
> + gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
> + }
> }
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index c137ac59e8..0ae00e10f6 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -42,6 +42,7 @@
> #include "hw/misc/xlnx-zynqmp-crf.h"
> #include "hw/timer/cadence_ttc.h"
> #include "hw/usb/hcd-dwc3.h"
> +#include "hw/core/split-irq.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -87,6 +88,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
>
> #define XLNX_ZYNQMP_NUM_TTC 4
> +#define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160
>
> /*
> * Unimplemented mmio regions needed to boot some images.
> @@ -105,6 +107,9 @@ struct XlnxZynqMPState {
> GICState gic;
> MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
>
> + GICState rpu_gic;
> + SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
> +
> MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
>
> MemoryRegion *ddr_ram;
> --
> 2.34.1
>
>
On Mon, 15 Sept 2025 at 09:59, Clément Chigot <chigot@adacore.com> wrote: > > From: Frederic Konrad <konrad.frederic@yahoo.fr> > > This wires a second GIC for the Cortex-R5, all the IRQs are split when there > is an RPU instanciated. > > Signed-off-by: Clément Chigot <chigot@adacore.com> > > --- > > Originally, this patch was member of a wider series. Other patches have > been merged since thus submit it back as a standalone patch. > https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg02328.html Note that I am assuming that one of the Xilinx folks will review this patch. thanks -- PMM
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