According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field:
altfmt for BF16 support.
This update changes the layout of the vtype CSR fields.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.h | 4 ++--
target/riscv/vector_helper.c | 29 ++++++++++++++++++++++++-----
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 738e68fa6e2..532386000af 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -190,8 +190,8 @@ FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
FIELD(VTYPE, VTA, 6, 1)
FIELD(VTYPE, VMA, 7, 1)
-FIELD(VTYPE, VEDIV, 8, 2)
-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
+FIELD(VTYPE, ALTFMT, 8, 1)
+FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10)
typedef struct PMUCTRState {
/* Current value of a counter */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7c67d67a13f..603d0731ae1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -33,6 +33,22 @@
#include "vector_internals.h"
#include <math.h>
+static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
+{
+ int xlen = riscv_cpu_xlen(env);
+ target_ulong reserved = 0;
+
+ if (riscv_cpu_cfg(env)->ext_zvfbfa) {
+ reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+ } else {
+ reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,
+ xlen - 1 - R_VTYPE_ALTFMT_SHIFT);
+ }
+
+ return reserved;
+}
+
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
target_ulong s2, target_ulong x0)
{
@@ -41,12 +57,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);
uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);
uint16_t sew = 8 << vsew;
- uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
+ uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);
int xlen = riscv_cpu_xlen(env);
bool vill = (s2 >> (xlen - 1)) & 0x1;
- target_ulong reserved = s2 &
- MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
- xlen - 1 - R_VTYPE_RESERVED_SHIFT);
uint16_t vlen = cpu->cfg.vlenb << 3;
int8_t lmul;
@@ -63,7 +76,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
}
}
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ if (cpu->cfg.ext_zvfbfa) {
+ if (altfmt == 1 && vsew >= MO_32) {
+ vill = true;
+ }
+ }
+
+ if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {
/* only set vill bit. */
env->vill = 1;
env->vtype = 0;
--
2.43.0
On 9/15/25 5:40 AM, Max Chou wrote:
> According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field:
> altfmt for BF16 support.
> This update changes the layout of the vtype CSR fields.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
> target/riscv/cpu.h | 4 ++--
> target/riscv/vector_helper.c | 29 ++++++++++++++++++++++++-----
> 2 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 738e68fa6e2..532386000af 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -190,8 +190,8 @@ FIELD(VTYPE, VLMUL, 0, 3)
> FIELD(VTYPE, VSEW, 3, 3)
> FIELD(VTYPE, VTA, 6, 1)
> FIELD(VTYPE, VMA, 7, 1)
> -FIELD(VTYPE, VEDIV, 8, 2)
> -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
> +FIELD(VTYPE, ALTFMT, 8, 1)
> +FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10)
>
> typedef struct PMUCTRState {
> /* Current value of a counter */
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 7c67d67a13f..603d0731ae1 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -33,6 +33,22 @@
> #include "vector_internals.h"
> #include <math.h>
>
> +static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
> +{
> + int xlen = riscv_cpu_xlen(env);
> + target_ulong reserved = 0;
> +
> + if (riscv_cpu_cfg(env)->ext_zvfbfa) {
> + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> + xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> + } else {
> + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,
> + xlen - 1 - R_VTYPE_ALTFMT_SHIFT);
> + }
Is this correct? The 'reserved' value you're returning when the new extension is enabled
is the original value from vsetvl:
> + if (riscv_cpu_cfg(env)->ext_zvfbfa) {
> + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> + xlen - 1 - R_VTYPE_RESERVED_SHIFT);
The original val you removed:
> - target_ulong reserved = s2 &
> - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> - xlen - 1 - R_VTYPE_RESERVED_SHIFT);
To preserve the existing behavior I believe you want to negate the conditional:
> + if (!riscv_cpu_cfg(env)->ext_zvfbfa) {
> + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> + xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> + } else {
> + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,
> + xlen - 1 - R_VTYPE_ALTFMT_SHIFT);
> + }
i.e. return the existing 'reserved' val if the new extension is absent, otherwise return
the new val.
Thanks,
Daniel
> +
> + return reserved;
> +}
> +
> target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> target_ulong s2, target_ulong x0)
> {
> @@ -41,12 +57,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);
> uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);
> uint16_t sew = 8 << vsew;
> - uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
> + uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);
> int xlen = riscv_cpu_xlen(env);
> bool vill = (s2 >> (xlen - 1)) & 0x1;
> - target_ulong reserved = s2 &
> - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> - xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> uint16_t vlen = cpu->cfg.vlenb << 3;
> int8_t lmul;
>
> @@ -63,7 +76,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> }
> }
>
> - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
> + if (cpu->cfg.ext_zvfbfa) {
> + if (altfmt == 1 && vsew >= MO_32) {
> + vill = true;
> + }
> + }
> +
> + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {
> /* only set vill bit. */
> env->vill = 1;
> env->vtype = 0;
On Wed, Sep 17, 2025 at 9:57 PM Daniel Henrique Barboza <
dbarboza@ventanamicro.com> wrote:
> Is this correct? The 'reserved' value you're returning when the new
> extension is enabled
> is the original value from vsetvl:
>
> > + if (riscv_cpu_cfg(env)->ext_zvfbfa) {
> > + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > + xlen - 1 -
> R_VTYPE_RESERVED_SHIFT);
>
> The original val you removed:
>
> > - target_ulong reserved = s2 &
> > - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > - xlen - 1 -
> R_VTYPE_RESERVED_SHIFT);
>
>
> To preserve the existing behavior I believe you want to negate the
> conditional:
>
> > + if (!riscv_cpu_cfg(env)->ext_zvfbfa) {
> > + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > + xlen - 1 -
> R_VTYPE_RESERVED_SHIFT);
> > + } else {
> > + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,
> > + xlen - 1 -
> R_VTYPE_ALTFMT_SHIFT);
> > + }
>
>
> i.e. return the existing 'reserved' val if the new extension is absent,
> otherwise return
> the new val.
>
>
> Thanks,
>
> Daniel
>
Hi Daniel,
Yes, I believe that’s correct. After enabling the Zvfbfa extension, the
reserved field in the VTYPE CSR depends on the extension as follows:
- When Zvfbfa is enabled:
- The reserved field in the VTYPE CSR: from bit 9 (VTYPE_RESERVED) to
XLEN
- When Zvfbfa is not enabled:
- The reserved field in the VTYPE CSR: from bit 8 (VTYPE_ALTFMT) to
XLEN
PS: This commit also modifies the definition of VTYPE_RESERVED.
Because the EDIV extension is not planned to be part of the base V
extension. Therefore, this commit modifies the default RESERVED field
definition.
Reference:
https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc
Thanks,
Max
>
>
> +
> > + return reserved;
> > +}
> > +
> > target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> > target_ulong s2, target_ulong x0)
> > {
> > @@ -41,12 +57,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env,
> target_ulong s1,
> > uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);
> > uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);
> > uint16_t sew = 8 << vsew;
> > - uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
> > + uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);
> > int xlen = riscv_cpu_xlen(env);
> > bool vill = (s2 >> (xlen - 1)) & 0x1;
> > - target_ulong reserved = s2 &
> > - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > - xlen - 1 -
> R_VTYPE_RESERVED_SHIFT);
> > uint16_t vlen = cpu->cfg.vlenb << 3;
> > int8_t lmul;
> >
> > @@ -63,7 +76,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env,
> target_ulong s1,
> > }
> > }
> >
> > - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved !=
> 0)) {
> > + if (cpu->cfg.ext_zvfbfa) {
> > + if (altfmt == 1 && vsew >= MO_32) {
> > + vill = true;
> > + }
> > + }
> > +
> > + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) !=
> 0)) {
> > /* only set vill bit. */
> > env->vill = 1;
> > env->vtype = 0;
>
>
On 9/22/25 5:03 AM, Max Chou wrote:
> On Wed, Sep 17, 2025 at 9:57 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com <mailto:dbarboza@ventanamicro.com>> wrote:
>
> Is this correct? The 'reserved' value you're returning when the new extension is enabled
> is the original value from vsetvl:
>
> > + if (riscv_cpu_cfg(env)->ext_zvfbfa) {
> > + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > + xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>
> The original val you removed:
>
> > - target_ulong reserved = s2 &
> > - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > - xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>
>
> To preserve the existing behavior I believe you want to negate the conditional:
>
> > + if (!riscv_cpu_cfg(env)->ext_zvfbfa) {
> > + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > + xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> > + } else {
> > + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,
> > + xlen - 1 - R_VTYPE_ALTFMT_SHIFT);
> > + }
>
>
> i.e. return the existing 'reserved' val if the new extension is absent, otherwise return
> the new val.
>
>
> Thanks,
>
> Daniel
>
> Hi Daniel,
>
>
> Yes, I believe that’s correct. After enabling the Zvfbfa extension, the reserved field in the VTYPE CSR depends on the extension as follows:
>
> * When Zvfbfa is enabled:
> o The reserved field in the VTYPE CSR: from bit 9 (VTYPE_RESERVED) to XLEN
> * When Zvfbfa is not enabled:
> o The reserved field in the VTYPE CSR: from bit 8 (VTYPE_ALTFMT) to XLEN
>
>
> PS: This commit also modifies the definition of VTYPE_RESERVED.
>
> Because the EDIV extension is not planned to be part of the base V extension. Therefore, this commit modifies the default RESERVED field definition.
>
>
> Reference: https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc <https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc>
Thanks for the info. That makes sense now. I suggest mentioning in the commit
msg that VTYPE_RESERVED was changed and the default value without Zvfbfa is
now different.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
>
> Thanks,
>
> Max
>
>
> > +
> > + return reserved;
> > +}
> > +
> > target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> > target_ulong s2, target_ulong x0)
> > {
> > @@ -41,12 +57,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> > uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);
> > uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);
> > uint16_t sew = 8 << vsew;
> > - uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
> > + uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);
> > int xlen = riscv_cpu_xlen(env);
> > bool vill = (s2 >> (xlen - 1)) & 0x1;
> > - target_ulong reserved = s2 &
> > - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> > - xlen - 1 - R_VTYPE_RESERVED_SHIFT);
> > uint16_t vlen = cpu->cfg.vlenb << 3;
> > int8_t lmul;
> >
> > @@ -63,7 +76,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> > }
> > }
> >
> > - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
> > + if (cpu->cfg.ext_zvfbfa) {
> > + if (altfmt == 1 && vsew >= MO_32) {
> > + vill = true;
> > + }
> > + }
> > +
> > + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {
> > /* only set vill bit. */
> > env->vill = 1;
> > env->vtype = 0;
>
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