This patch series adds Zvfbfa extension support.

The isa spec of Zvfbfa extension is not ratified yet, so this patch series
is based on the latest draft of the spec (v0.1) and make the Zvfbfa extension
as an experimental extension.

The draft of the Zvfbfa isa spec:
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc

Max Chou (8):
  target/riscv: Add cfg properities for Zvfbfa extensions
  target/riscv: Add the Zvfbfa extension implied rule
  target/riscv: rvv: Add new VTYPE CSR field - altfmt
  target/riscv: Use the tb->cs_bqse as the extend tb flags.
  target/riscv: Introduce altfmt into DisasContext
  target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension
  target/riscv: rvv: Support Zvfbfa vector bf16 operations
  target/riscv: Expose Zvfbfa extension as an experimental cpu property

 include/exec/translation-block.h           |   1 +
 target/riscv/cpu.c                         |  15 +-
 target/riscv/cpu.h                         |   6 +-
 target/riscv/cpu_cfg_fields.h.inc          |   1 +
 target/riscv/helper.h                      |  60 ++
 target/riscv/insn_trans/trans_rvbf16.c.inc |   2 +-
 target/riscv/insn_trans/trans_rvv.c.inc    | 992 +++++++++++++--------
 target/riscv/internals.h                   |   1 +
 target/riscv/tcg/tcg-cpu.c                 |  14 +-
 target/riscv/translate.c                   |  11 +
 target/riscv/vector_helper.c               | 358 +++++++-
 11 files changed, 1064 insertions(+), 397 deletions(-)

-- 
2.43.0