Introduces flags and register definitions needed
for the IBM PPE42 exception model.
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
---
target/ppc/cpu.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8e13ce41a9..787020f6f9 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -220,6 +220,8 @@ typedef enum powerpc_excp_t {
POWERPC_EXCP_POWER10,
/* POWER11 exception model */
POWERPC_EXCP_POWER11,
+ /* PPE42 exception model */
+ POWERPC_EXCP_PPE42,
} powerpc_excp_t;
/*****************************************************************************/
@@ -760,6 +762,31 @@ FIELD(MSR, SIBRCA, MSR_SIBRCA7, 8)
#define ESR_VLEMI PPC_BIT(58) /* VLE operation */
#define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
+/* PPE42 Interrupt Status Register bits */
+#define PPE42_ISR_SRSMS0 PPC_BIT_NR(48) /* Sys Reset State Machine State 0 */
+#define PPE42_ISR_SRSMS1 PPC_BIT_NR(49) /* Sys Reset State Machine State 1 */
+#define PPE42_ISR_SRSMS2 PPC_BIT_NR(50) /* Sys Reset State Machine State 2 */
+#define PPE42_ISR_SRSMS3 PPC_BIT_NR(51) /* Sys Reset State Machine State 3 */
+#define PPE42_ISR_EP PPC_BIT_NR(53) /* MSR[EE] Maskable Event Pending */
+#define PPE42_ISR_PTR PPC_BIT_NR(56) /* Program Interrupt from trap */
+#define PPE42_ISR_ST PPC_BIT_NR(57) /* Data Interrupt caused by store */
+#define PPE42_ISR_MFE PPC_BIT_NR(60) /* Multiple Fault Error */
+#define PPE42_ISR_MCS0 PPC_BIT_NR(61) /* Machine Check Status bit0 */
+#define PPE42_ISR_MCS1 PPC_BIT_NR(62) /* Machine Check Status bit1 */
+#define PPE42_ISR_MCS2 PPC_BIT_NR(63) /* Machine Check Status bit2 */
+FIELD(PPE42_ISR, SRSMS, PPE42_ISR_SRSMS3, 4)
+FIELD(PPE42_ISR, MCS, PPE42_ISR_MCS2, 3)
+
+/* PPE42 Machine Check Status field values */
+#define PPE42_ISR_MCS_INSTRUCTION 0
+#define PPE42_ISR_MCS_DATA_LOAD 1
+#define PPE42_ISR_MCS_DATA_PRECISE_STORE 2
+#define PPE42_ISR_MCS_DATA_IMPRECISE_STORE 3
+#define PPE42_ISR_MCS_PROGRAM 4
+#define PPE42_ISR_MCS_ISI 5
+#define PPE42_ISR_MCS_ALIGNMENT 6
+#define PPE42_ISR_MCS_DSI 7
+
/* Transaction EXception And Summary Register bits */
#define TEXASR_FAILURE_PERSISTENT (63 - 7)
#define TEXASR_DISALLOWED (63 - 8)
--
2.43.0