On 9/11/25 09:24, Jamin Lin wrote:
> Add PCIe controller and PHY instances to the Aspeed SoC state and device
> enum. This prepares the SoC model to host PCIe Root Complexes and their
> associated PHYs.
>
> Although the AST2600 supports only a single Root Complex, the AST2700
> provides three Root Complexes. For this reason, the model defines arrays
> of three PCIe config/PHY objects and enumerates three PCIe device IDs so
> that both SoCs can be represented consistently.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 217ef0eafd..79fe353f83 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -37,6 +37,7 @@
> #include "qom/object.h"
> #include "hw/misc/aspeed_lpc.h"
> #include "hw/misc/unimp.h"
> +#include "hw/pci-host/aspeed_pcie.h"
> #include "hw/misc/aspeed_peci.h"
> #include "hw/fsi/aspeed_apb2opb.h"
> #include "hw/char/serial-mm.h"
> @@ -49,6 +50,7 @@
> #define ASPEED_MACS_NUM 4
> #define ASPEED_UARTS_NUM 13
> #define ASPEED_JTAG_NUM 2
> +#define ASPEED_PCIE_NUM 3
>
> struct AspeedSoCState {
> DeviceState parent;
> @@ -87,6 +89,8 @@ struct AspeedSoCState {
> AspeedSDHCIState sdhci;
> AspeedSDHCIState emmc;
> AspeedLPCState lpc;
> + AspeedPCIECfgState pcie[ASPEED_PCIE_NUM];
> + AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM];
> AspeedPECIState peci;
> SerialMM uart[ASPEED_UARTS_NUM];
> Clock *sysclk;
> @@ -254,6 +258,15 @@ enum {
> ASPEED_DEV_LPC,
> ASPEED_DEV_IBT,
> ASPEED_DEV_I2C,
> + ASPEED_DEV_PCIE0,
> + ASPEED_DEV_PCIE1,
> + ASPEED_DEV_PCIE2,
> + ASPEED_DEV_PCIE_PHY0,
> + ASPEED_DEV_PCIE_PHY1,
> + ASPEED_DEV_PCIE_PHY2,
> + ASPEED_DEV_PCIE_MMIO0,
> + ASPEED_DEV_PCIE_MMIO1,
> + ASPEED_DEV_PCIE_MMIO2,
> ASPEED_DEV_PECI,
> ASPEED_DEV_ETH1,
> ASPEED_DEV_ETH2,