[v3] Fix RISC-V timer migration issues

[PATCH v3 0/4] Fix RISC-V timer migration issues

Posted by TANG Tiancheng 4 months, 4 weeks ago

This patch set fixes several timer-related migration issues in QEMU's
RISC-V implementation that cause timer events to be lost or behave
incorrectly after snapshot save/restore or live migration.

The problems addressed are:

1. ACLINT mtimer time_delta not migrated: The time_delta field in
RISCVAclintMTimerState was missing from vmstate, causing incorrect
mtime values after snapshot restore. This resulted in guest time
appearing "frozen" until enough virtual time elapsed to compensate
for the offset error.

2. ACLINT mtimer timers array not migrated: Active timer events
scheduled via riscv_aclint_mtimer_write_timecmp() were not being
migrated, causing pending timer interrupts to be lost after restore.

3. CPU stimer/vstimer not migrated: The S-mode and VS-mode timer
pointers in CPURISCVState were missing from vmstate_riscv_cpu,
causing supervisor-level timer events to be lost.

The patch set introduces a new VMSTATE_TIMER_PTR_VARRAY macro to handle
migration of variable-length timer pointer arrays, and adds the missing
timer fields to the appropriate vmstate structures.

Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
---
Changes in v3:
- Remove 'include/' of the subject at patch v2 2/4.
- Added Reviewed-by from Peter Xu.
- Link to v2: https://lore.kernel.org/qemu-devel/20250910-timers-v2-0-31359f1f6ee8@linux.alibaba.com

Changes in v2:
- Split VMSTATE_VARRAY_OF_POINTER_UINT32() into a separate patch,
and define VMSTATE_TIMER_PTR_VARRAY() in riscv_aclint.h.
- Added Reviewed-by from Daniel Henrique Barboza.
- Link to v1: https://lore.kernel.org/qemu-devel/20250909-timers-v1-0-7ee18a9d8f4b@linux.alibaba.com

---
TANG Tiancheng (4):
hw/intc: Save time_delta in RISC-V mtimer VMState
migration: Add support for a variable-length array of UINT32 pointers
hw/intc: Save timers array in RISC-V mtimer VMState
target/riscv: Save stimer and vstimer in CPU vmstate

hw/intc/riscv_aclint.c | 7 +++++--
include/hw/intc/riscv_aclint.h | 4 ++++
include/migration/vmstate.h | 10 ++++++++++
target/riscv/machine.c | 25 +++++++++++++++++++++++++
4 files changed, 44 insertions(+), 2 deletions(-)
---
base-commit: 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8
change-id: 20250909-timers-18c2c67b1a2a

Best regards,
--
TANG Tiancheng <lyndra@linux.alibaba.com>

Re: [PATCH v3 0/4] Fix RISC-V timer migration issues

Posted by Michael Tokarev 4 months, 1 week ago

On 9/11/25 12:56, TANG Tiancheng wrote:
> This patch set fixes several timer-related migration issues in QEMU's
> RISC-V implementation that cause timer events to be lost or behave
> incorrectly after snapshot save/restore or live migration.
> 
> The problems addressed are:
> 
> 1. ACLINT mtimer time_delta not migrated: The time_delta field in
>     RISCVAclintMTimerState was missing from vmstate, causing incorrect
>     mtime values after snapshot restore. This resulted in guest time
>     appearing "frozen" until enough virtual time elapsed to compensate
>     for the offset error.
> 
> 2. ACLINT mtimer timers array not migrated: Active timer events
>     scheduled via riscv_aclint_mtimer_write_timecmp() were not being
>     migrated, causing pending timer interrupts to be lost after restore.
> 
> 3. CPU stimer/vstimer not migrated: The S-mode and VS-mode timer
>     pointers in CPURISCVState were missing from vmstate_riscv_cpu,
>     causing supervisor-level timer events to be lost.
> 
> The patch set introduces a new VMSTATE_TIMER_PTR_VARRAY macro to handle
> migration of variable-length timer pointer arrays, and adds the missing
> timer fields to the appropriate vmstate structures.
> 
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> ---
> Changes in v3:
> - Remove 'include/' of the subject at patch v2 2/4.
> - Added Reviewed-by from Peter Xu.
> - Link to v2: https://lore.kernel.org/qemu-devel/20250910-timers-v2-0-31359f1f6ee8@linux.alibaba.com
> 
> Changes in v2:
> - Split VMSTATE_VARRAY_OF_POINTER_UINT32() into a separate patch,
>    and define VMSTATE_TIMER_PTR_VARRAY() in riscv_aclint.h.
> - Added Reviewed-by from Daniel Henrique Barboza.
> - Link to v1: https://lore.kernel.org/qemu-devel/20250909-timers-v1-0-7ee18a9d8f4b@linux.alibaba.com
> 
> ---
> TANG Tiancheng (4):
>        hw/intc: Save time_delta in RISC-V mtimer VMState
>        migration: Add support for a variable-length array of UINT32 pointers
>        hw/intc: Save timers array in RISC-V mtimer VMState
>        target/riscv: Save stimer and vstimer in CPU vmstate

Am I right this stuff is not back-portable to previous qemu
stable releases, as it introduces new fields into the migration
stream which, which can't be picked up by these releases?

 From the description it seems like all this stuff should be fixed
in previous stable qemu releases too.

Thanks,

/mjt

Re: [PATCH v3 0/4] Fix RISC-V timer migration issues

Posted by Alistair Francis 4 months ago

On Sat, Oct 4, 2025 at 5:19 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> On 9/11/25 12:56, TANG Tiancheng wrote:
> > This patch set fixes several timer-related migration issues in QEMU's
> > RISC-V implementation that cause timer events to be lost or behave
> > incorrectly after snapshot save/restore or live migration.
> >
> > The problems addressed are:
> >
> > 1. ACLINT mtimer time_delta not migrated: The time_delta field in
> >     RISCVAclintMTimerState was missing from vmstate, causing incorrect
> >     mtime values after snapshot restore. This resulted in guest time
> >     appearing "frozen" until enough virtual time elapsed to compensate
> >     for the offset error.
> >
> > 2. ACLINT mtimer timers array not migrated: Active timer events
> >     scheduled via riscv_aclint_mtimer_write_timecmp() were not being
> >     migrated, causing pending timer interrupts to be lost after restore.
> >
> > 3. CPU stimer/vstimer not migrated: The S-mode and VS-mode timer
> >     pointers in CPURISCVState were missing from vmstate_riscv_cpu,
> >     causing supervisor-level timer events to be lost.
> >
> > The patch set introduces a new VMSTATE_TIMER_PTR_VARRAY macro to handle
> > migration of variable-length timer pointer arrays, and adds the missing
> > timer fields to the appropriate vmstate structures.
> >
> > Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> > ---
> > Changes in v3:
> > - Remove 'include/' of the subject at patch v2 2/4.
> > - Added Reviewed-by from Peter Xu.
> > - Link to v2: https://lore.kernel.org/qemu-devel/20250910-timers-v2-0-31359f1f6ee8@linux.alibaba.com
> >
> > Changes in v2:
> > - Split VMSTATE_VARRAY_OF_POINTER_UINT32() into a separate patch,
> >    and define VMSTATE_TIMER_PTR_VARRAY() in riscv_aclint.h.
> > - Added Reviewed-by from Daniel Henrique Barboza.
> > - Link to v1: https://lore.kernel.org/qemu-devel/20250909-timers-v1-0-7ee18a9d8f4b@linux.alibaba.com
> >
> > ---
> > TANG Tiancheng (4):
> >        hw/intc: Save time_delta in RISC-V mtimer VMState
> >        migration: Add support for a variable-length array of UINT32 pointers
> >        hw/intc: Save timers array in RISC-V mtimer VMState
> >        target/riscv: Save stimer and vstimer in CPU vmstate
>
> Am I right this stuff is not back-portable to previous qemu
> stable releases, as it introduces new fields into the migration
> stream which, which can't be picked up by these releases?

Yes, I don't think this should be backported as it'stargetting migration.

Alistair

>
>  From the description it seems like all this stuff should be fixed
> in previous stable qemu releases too.
>
> Thanks,
>
> /mjt
>

Re: [PATCH v3 0/4] Fix RISC-V timer migration issues

Posted by Alistair Francis 4 months, 3 weeks ago

On Thu, Sep 11, 2025 at 7:59 PM TANG Tiancheng <lyndra@linux.alibaba.com> wrote:
>
> This patch set fixes several timer-related migration issues in QEMU's
> RISC-V implementation that cause timer events to be lost or behave
> incorrectly after snapshot save/restore or live migration.
>
> The problems addressed are:
>
> 1. ACLINT mtimer time_delta not migrated: The time_delta field in
>    RISCVAclintMTimerState was missing from vmstate, causing incorrect
>    mtime values after snapshot restore. This resulted in guest time
>    appearing "frozen" until enough virtual time elapsed to compensate
>    for the offset error.
>
> 2. ACLINT mtimer timers array not migrated: Active timer events
>    scheduled via riscv_aclint_mtimer_write_timecmp() were not being
>    migrated, causing pending timer interrupts to be lost after restore.
>
> 3. CPU stimer/vstimer not migrated: The S-mode and VS-mode timer
>    pointers in CPURISCVState were missing from vmstate_riscv_cpu,
>    causing supervisor-level timer events to be lost.
>
> The patch set introduces a new VMSTATE_TIMER_PTR_VARRAY macro to handle
> migration of variable-length timer pointer arrays, and adds the missing
> timer fields to the appropriate vmstate structures.
>
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Changes in v3:
> - Remove 'include/' of the subject at patch v2 2/4.
> - Added Reviewed-by from Peter Xu.
> - Link to v2: https://lore.kernel.org/qemu-devel/20250910-timers-v2-0-31359f1f6ee8@linux.alibaba.com
>
> Changes in v2:
> - Split VMSTATE_VARRAY_OF_POINTER_UINT32() into a separate patch,
>   and define VMSTATE_TIMER_PTR_VARRAY() in riscv_aclint.h.
> - Added Reviewed-by from Daniel Henrique Barboza.
> - Link to v1: https://lore.kernel.org/qemu-devel/20250909-timers-v1-0-7ee18a9d8f4b@linux.alibaba.com
>
> ---
> TANG Tiancheng (4):
>       hw/intc: Save time_delta in RISC-V mtimer VMState
>       migration: Add support for a variable-length array of UINT32 pointers
>       hw/intc: Save timers array in RISC-V mtimer VMState
>       target/riscv: Save stimer and vstimer in CPU vmstate
>
>  hw/intc/riscv_aclint.c         |  7 +++++--
>  include/hw/intc/riscv_aclint.h |  4 ++++
>  include/migration/vmstate.h    | 10 ++++++++++
>  target/riscv/machine.c         | 25 +++++++++++++++++++++++++
>  4 files changed, 44 insertions(+), 2 deletions(-)
> ---
> base-commit: 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8
> change-id: 20250909-timers-18c2c67b1a2a
>
> Best regards,
> --
> TANG Tiancheng <lyndra@linux.alibaba.com>
>
>