[v1] Fix RISC-V timer migration issues

[PATCH 0/3] Fix RISC-V timer migration issues

TANG Tiancheng posted 3 patches 2 weeks, 5 days ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Peter Xu <peterx@redhat.com>, Fabiano Rosas <farosas@suse.de>

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hw/intc/riscv_aclint.c      |  7 +++++--
include/migration/vmstate.h | 14 ++++++++++++++
target/riscv/machine.c      | 25 +++++++++++++++++++++++++
3 files changed, 44 insertions(+), 2 deletions(-)

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[PATCH 0/3] Fix RISC-V timer migration issues

Posted by TANG Tiancheng 2 weeks, 5 days ago

This patch set fixes several timer-related migration issues in QEMU's
RISC-V implementation that cause timer events to be lost or behave
incorrectly after snapshot save/restore or live migration.

The problems addressed are:

1. ACLINT mtimer time_delta not migrated: The time_delta field in
   RISCVAclintMTimerState was missing from vmstate, causing incorrect
   mtime values after snapshot restore. This resulted in guest time
   appearing "frozen" until enough virtual time elapsed to compensate
   for the offset error.

2. ACLINT mtimer timers array not migrated: Active timer events
   scheduled via riscv_aclint_mtimer_write_timecmp() were not being
   migrated, causing pending timer interrupts to be lost after restore.

3. CPU stimer/vstimer not migrated: The S-mode and VS-mode timer
   pointers in CPURISCVState were missing from vmstate_riscv_cpu,
   causing supervisor-level timer events to be lost.

The patch set introduces a new VMSTATE_TIMER_PTR_VARRAY macro to handle
migration of variable-length timer pointer arrays, and adds the missing
timer fields to the appropriate vmstate structures.

Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
---
TANG Tiancheng (3):
      hw/intc: Save time_delta in RISC-V mtimer VMState
      hw/intc: Save timers array in RISC-V mtimer VMState
      target/riscv: Save stimer and vstimer in CPU vmstate

 hw/intc/riscv_aclint.c      |  7 +++++--
 include/migration/vmstate.h | 14 ++++++++++++++
 target/riscv/machine.c      | 25 +++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 2 deletions(-)
---
base-commit: 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8
change-id: 20250909-timers-18c2c67b1a2a

Best regards,
-- 
TANG Tiancheng <lyndra@linux.alibaba.com>