[PATCH v4 12/13] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()

Bibo Mao posted 13 patches 7 hours ago
Maintainers: Song Gao <gaosong@loongson.cn>
[PATCH v4 12/13] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()
Posted by Bibo Mao 7 hours ago
With function helper_invtlb_page_asid_or_g(), only one TLB entry in
LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
necessary to flush all QEMU TLB, only flush address range specified
LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
so that only QEMU TLB entry with specified address range is flushed.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/loongarch/tcg/tlb_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index b777f68f71..243f945612 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -556,8 +556,7 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
     func = tlb_match_any;
     tlb = loongarch_tlb_search_cb(env, addr, asid, func);
     if (tlb) {
-        tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
-        tlb_flush(env_cpu(env));
+        invalidate_tlb(env, tlb - env->tlb);
     }
 }
 
-- 
2.39.3